Lines Matching +full:uniphier +full:- +full:ld20 +full:- +full:usb3 +full:- +full:regulator
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-ssphy
22 - socionext,uniphier-pro5-usb3-ssphy
23 - socionext,uniphier-pxs2-usb3-ssphy
24 - socionext,uniphier-ld20-usb3-ssphy
25 - socionext,uniphier-pxs3-usb3-ssphy
26 - socionext,uniphier-nx1-usb3-ssphy
31 "#phy-cells":
38 clock-names:
45 reset-names:
48 vbus-supply:
49 description: A phandle to the regulator for USB VBUS, only for USB host
52 - if:
57 - socionext,uniphier-pro4-usb3-ssphy
58 - socionext,uniphier-pro5-usb3-ssphy
64 clock-names:
66 - const: gio
67 - const: link
71 reset-names:
73 - const: gio
74 - const: link
75 - if:
80 - socionext,uniphier-pxs2-usb3-ssphy
81 - socionext,uniphier-ld20-usb3-ssphy
87 clock-names:
89 - const: link
90 - const: phy
94 reset-names:
96 - const: link
97 - const: phy
98 - if:
103 - socionext,uniphier-pxs3-usb3-ssphy
104 - socionext,uniphier-nx1-usb3-ssphy
110 clock-names:
113 - const: link
114 - const: phy
115 - const: phy-ext
119 reset-names:
121 - const: link
122 - const: phy
125 - compatible
126 - reg
127 - "#phy-cells"
128 - clocks
129 - clock-names
130 - resets
131 - reset-names
136 - |
138 compatible = "socionext,uniphier-ld20-usb3-ssphy";
140 #phy-cells = <0>;
141 clock-names = "link", "phy";
143 reset-names = "link", "phy";
145 vbus-supply = <&usb_vbus0>;