Lines Matching +full:pcie +full:- +full:phy +full:- +full:1

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe PHY
10   This describes the devicetree bindings for PHY interface built into
11   PCIe controller implemented on Socionext UniPhier SoCs.
14   - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19       - socionext,uniphier-pro5-pcie-phy
20       - socionext,uniphier-ld20-pcie-phy
21       - socionext,uniphier-pxs3-pcie-phy
22       - socionext,uniphier-nx1-pcie-phy
25     maxItems: 1
27   "#phy-cells":
31     minItems: 1
34   clock-names:
35     minItems: 1
39     minItems: 1
42   reset-names:
43     minItems: 1
48     description: A phandle to system control to set configurations for phy
51   - if:
55             const: socionext,uniphier-pro5-pcie-phy
61         clock-names:
63             - const: gio
64             - const: link
68         reset-names:
70             - const: gio
71             - const: link
75           maxItems: 1
76         clock-names:
79           maxItems: 1
80         reset-names:
84   - compatible
85   - reg
86   - "#phy-cells"
87   - clocks
88   - clock-names
89   - resets
90   - reset-names
95   - |
96     pcie_phy: phy@66038000 {
97         compatible = "socionext,uniphier-ld20-pcie-phy";
99         #phy-cells = <0>;
100         clock-names = "link";
102         reset-names = "link";