Lines Matching +full:gcc +full:- +full:qcs404

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
10   - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
13   Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY
18       - qcom,usb-hs-28nm-femtophy
23   "#phy-cells":
28       - description: rpmcc ref clock
29       - description: PHY AHB clock
30       - description: Rentention clock
32   clock-names:
34       - const: ref
35       - const: ahb
36       - const: sleep
40       - description: PHY core reset
41       - description: POR reset
43   reset-names:
45       - const: phy
46       - const: por
48   vdd-supply:
51   vdda1p8-supply:
54   vdda3p3-supply:
58   - compatible
59   - reg
60   - "#phy-cells"
61   - clocks
62   - clock-names
63   - resets
64   - reset-names
65   - vdd-supply
66   - vdda1p8-supply
67   - vdda3p3-supply
72   - |
73     #include <dt-bindings/clock/qcom,gcc-qcs404.h>
74     #include <dt-bindings/clock/qcom,rpmcc.h>
76         compatible = "qcom,usb-hs-28nm-femtophy";
78         #phy-cells = <0>;
80                  <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
81                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
82         clock-names = "ref", "ahb", "sleep";
83         resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
84                  <&gcc GCC_USB2A_PHY_BCR>;
85         reset-names = "phy", "por";
86         vdd-supply = <&vreg_l4_1p2>;
87         vdda1p8-supply = <&vreg_l5_1p8>;
88         vdda3p3-supply = <&vreg_l12_3p3>;