Lines Matching +full:phy +full:- +full:names
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,qcs615-qmp-gen3x1-pcie-phy
20 - qcom,qcs8300-qmp-gen4x2-pcie-phy
21 - qcom,sa8775p-qmp-gen4x2-pcie-phy
22 - qcom,sa8775p-qmp-gen4x4-pcie-phy
23 - qcom,sar2130p-qmp-gen3x2-pcie-phy
24 - qcom,sc8180x-qmp-pcie-phy
25 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
26 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
27 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
28 - qcom,sdm845-qhp-pcie-phy
29 - qcom,sdm845-qmp-pcie-phy
30 - qcom,sdx55-qmp-pcie-phy
31 - qcom,sdx65-qmp-gen4x2-pcie-phy
32 - qcom,sm8150-qmp-gen3x1-pcie-phy
33 - qcom,sm8150-qmp-gen3x2-pcie-phy
34 - qcom,sm8250-qmp-gen3x1-pcie-phy
35 - qcom,sm8250-qmp-gen3x2-pcie-phy
36 - qcom,sm8250-qmp-modem-pcie-phy
37 - qcom,sm8350-qmp-gen3x1-pcie-phy
38 - qcom,sm8350-qmp-gen3x2-pcie-phy
39 - qcom,sm8450-qmp-gen3x1-pcie-phy
40 - qcom,sm8450-qmp-gen4x2-pcie-phy
41 - qcom,sm8550-qmp-gen3x2-pcie-phy
42 - qcom,sm8550-qmp-gen4x2-pcie-phy
43 - qcom,sm8650-qmp-gen3x2-pcie-phy
44 - qcom,sm8650-qmp-gen4x2-pcie-phy
45 - qcom,x1e80100-qmp-gen3x2-pcie-phy
46 - qcom,x1e80100-qmp-gen4x2-pcie-phy
47 - qcom,x1e80100-qmp-gen4x4-pcie-phy
48 - qcom,x1e80100-qmp-gen4x8-pcie-phy
49 - qcom,x1p42100-qmp-gen4x4-pcie-phy
59 clock-names:
62 - const: aux
63 - const: cfg_ahb
64 - const: ref
65 - enum: [rchng, refgen]
66 - const: pipe
67 - const: pipediv2
68 - const: phy_aux
70 power-domains:
77 reset-names:
80 - const: phy
81 - const: phy_nocsr
83 vdda-phy-supply: true
85 vdda-pll-supply: true
87 vdda-qref-supply: true
89 qcom,4ln-config-sel:
90 description: PCIe 4-lane configuration
91 $ref: /schemas/types.yaml#/definitions/phandle-array
93 - items:
94 - description: phandle of TCSR syscon
95 - description: offset of PCIe 4-lane configuration register
96 - description: offset of configuration bit for this PHY
98 "#clock-cells": true
100 clock-output-names:
103 "#phy-cells":
107 - compatible
108 - reg
109 - clocks
110 - clock-names
111 - resets
112 - reset-names
113 - vdda-phy-supply
114 - vdda-pll-supply
115 - "#clock-cells"
116 - clock-output-names
117 - "#phy-cells"
122 - if:
127 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
128 - qcom,x1e80100-qmp-gen4x4-pcie-phy
129 - qcom,x1p42100-qmp-gen4x4-pcie-phy
134 - description: port a
135 - description: port b
137 - qcom,4ln-config-sel
143 - if:
148 - qcom,qcs615-qmp-gen3x1-pcie-phy
149 - qcom,sar2130p-qmp-gen3x2-pcie-phy
150 - qcom,sc8180x-qmp-pcie-phy
151 - qcom,sdm845-qhp-pcie-phy
152 - qcom,sdm845-qmp-pcie-phy
153 - qcom,sdx55-qmp-pcie-phy
154 - qcom,sm8150-qmp-gen3x1-pcie-phy
155 - qcom,sm8150-qmp-gen3x2-pcie-phy
156 - qcom,sm8250-qmp-gen3x1-pcie-phy
157 - qcom,sm8250-qmp-gen3x2-pcie-phy
158 - qcom,sm8250-qmp-modem-pcie-phy
159 - qcom,sm8350-qmp-gen3x1-pcie-phy
160 - qcom,sm8350-qmp-gen3x2-pcie-phy
161 - qcom,sm8450-qmp-gen3x1-pcie-phy
162 - qcom,sm8450-qmp-gen3x2-pcie-phy
163 - qcom,sm8550-qmp-gen3x2-pcie-phy
164 - qcom,sm8550-qmp-gen4x2-pcie-phy
165 - qcom,sm8650-qmp-gen3x2-pcie-phy
166 - qcom,sm8650-qmp-gen4x2-pcie-phy
171 clock-names:
174 - if:
179 - qcom,sa8775p-qmp-gen4x2-pcie-phy
180 - qcom,sa8775p-qmp-gen4x4-pcie-phy
181 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
182 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
183 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
184 - qcom,x1e80100-qmp-gen3x2-pcie-phy
185 - qcom,x1e80100-qmp-gen4x2-pcie-phy
186 - qcom,x1e80100-qmp-gen4x4-pcie-phy
187 - qcom,x1e80100-qmp-gen4x8-pcie-phy
188 - qcom,x1p42100-qmp-gen4x4-pcie-phy
193 clock-names:
196 - if:
201 - qcom,qcs8300-qmp-gen4x2-pcie-phy
206 clock-names:
209 - if:
214 - qcom,sm8550-qmp-gen4x2-pcie-phy
215 - qcom,sm8650-qmp-gen4x2-pcie-phy
216 - qcom,x1e80100-qmp-gen4x2-pcie-phy
217 - qcom,x1e80100-qmp-gen4x4-pcie-phy
218 - qcom,x1e80100-qmp-gen4x8-pcie-phy
223 reset-names:
226 - if:
231 - qcom,sm8450-qmp-gen4x2-pcie-phy
232 - qcom,sm8550-qmp-gen4x2-pcie-phy
233 - qcom,sm8650-qmp-gen4x2-pcie-phy
236 "#clock-cells":
240 "#clock-cells":
244 - |
245 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
247 pcie2b_phy: phy@1c18000 {
248 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
257 clock-names = "aux", "cfg_ahb", "ref", "rchng",
260 power-domains = <&gcc PCIE_2B_GDSC>;
263 reset-names = "phy";
265 vdda-phy-supply = <&vreg_l6d>;
266 vdda-pll-supply = <&vreg_l4d>;
268 #clock-cells = <0>;
269 clock-output-names = "pcie_2b_pipe_clk";
271 #phy-cells = <0>;
274 pcie2a_phy: phy@1c24000 {
275 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
284 clock-names = "aux", "cfg_ahb", "ref", "rchng",
287 power-domains = <&gcc PCIE_2A_GDSC>;
290 reset-names = "phy";
292 vdda-phy-supply = <&vreg_l6d>;
293 vdda-pll-supply = <&vreg_l4d>;
295 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
297 #clock-cells = <0>;
298 clock-output-names = "pcie_2a_pipe_clk";
300 #phy-cells = <0>;