Lines Matching +full:gcc +full:- +full:sdm845
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
22 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
23 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
24 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
25 - qcom,sdm845-qhp-pcie-phy
26 - qcom,sdm845-qmp-pcie-phy
27 - qcom,sdx55-qmp-pcie-phy
28 - qcom,sdx65-qmp-gen4x2-pcie-phy
29 - qcom,sm8150-qmp-gen3x1-pcie-phy
30 - qcom,sm8150-qmp-gen3x2-pcie-phy
31 - qcom,sm8250-qmp-gen3x1-pcie-phy
32 - qcom,sm8250-qmp-gen3x2-pcie-phy
33 - qcom,sm8250-qmp-modem-pcie-phy
34 - qcom,sm8350-qmp-gen3x1-pcie-phy
35 - qcom,sm8450-qmp-gen3x1-pcie-phy
36 - qcom,sm8450-qmp-gen4x2-pcie-phy
37 - qcom,sm8550-qmp-gen3x2-pcie-phy
38 - qcom,sm8550-qmp-gen4x2-pcie-phy
39 - qcom,sm8650-qmp-gen3x2-pcie-phy
40 - qcom,sm8650-qmp-gen4x2-pcie-phy
41 - qcom,x1e80100-qmp-gen3x2-pcie-phy
42 - qcom,x1e80100-qmp-gen4x2-pcie-phy
43 - qcom,x1e80100-qmp-gen4x4-pcie-phy
53 clock-names:
56 - const: aux
57 - const: cfg_ahb
58 - const: ref
59 - enum: [rchng, refgen]
60 - const: pipe
61 - const: pipediv2
62 - const: phy_aux
64 power-domains:
71 reset-names:
74 - const: phy
75 - const: phy_nocsr
77 vdda-phy-supply: true
79 vdda-pll-supply: true
81 vdda-qref-supply: true
83 qcom,4ln-config-sel:
84 description: PCIe 4-lane configuration
85 $ref: /schemas/types.yaml#/definitions/phandle-array
87 - items:
88 - description: phandle of TCSR syscon
89 - description: offset of PCIe 4-lane configuration register
90 - description: offset of configuration bit for this PHY
92 "#clock-cells": true
94 clock-output-names:
97 "#phy-cells":
101 - compatible
102 - reg
103 - clocks
104 - clock-names
105 - resets
106 - reset-names
107 - vdda-phy-supply
108 - vdda-pll-supply
109 - "#clock-cells"
110 - clock-output-names
111 - "#phy-cells"
116 - if:
121 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
122 - qcom,x1e80100-qmp-gen4x4-pcie-phy
127 - description: port a
128 - description: port b
130 - qcom,4ln-config-sel
136 - if:
141 - qcom,sc8180x-qmp-pcie-phy
142 - qcom,sdm845-qhp-pcie-phy
143 - qcom,sdm845-qmp-pcie-phy
144 - qcom,sdx55-qmp-pcie-phy
145 - qcom,sm8150-qmp-gen3x1-pcie-phy
146 - qcom,sm8150-qmp-gen3x2-pcie-phy
147 - qcom,sm8250-qmp-gen3x1-pcie-phy
148 - qcom,sm8250-qmp-gen3x2-pcie-phy
149 - qcom,sm8250-qmp-modem-pcie-phy
150 - qcom,sm8350-qmp-gen3x1-pcie-phy
151 - qcom,sm8450-qmp-gen3x1-pcie-phy
152 - qcom,sm8450-qmp-gen3x2-pcie-phy
153 - qcom,sm8550-qmp-gen3x2-pcie-phy
154 - qcom,sm8550-qmp-gen4x2-pcie-phy
155 - qcom,sm8650-qmp-gen3x2-pcie-phy
156 - qcom,sm8650-qmp-gen4x2-pcie-phy
161 clock-names:
164 - if:
169 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
170 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
171 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
172 - qcom,x1e80100-qmp-gen3x2-pcie-phy
173 - qcom,x1e80100-qmp-gen4x2-pcie-phy
174 - qcom,x1e80100-qmp-gen4x4-pcie-phy
179 clock-names:
182 - if:
187 - qcom,sa8775p-qmp-gen4x2-pcie-phy
188 - qcom,sa8775p-qmp-gen4x4-pcie-phy
193 clock-names:
196 - if:
201 - qcom,sm8550-qmp-gen4x2-pcie-phy
202 - qcom,sm8650-qmp-gen4x2-pcie-phy
203 - qcom,x1e80100-qmp-gen4x2-pcie-phy
204 - qcom,x1e80100-qmp-gen4x4-pcie-phy
209 reset-names:
215 reset-names:
218 - if:
223 - qcom,sm8450-qmp-gen4x2-pcie-phy
224 - qcom,sm8550-qmp-gen4x2-pcie-phy
225 - qcom,sm8650-qmp-gen4x2-pcie-phy
228 "#clock-cells":
232 "#clock-cells":
236 - |
237 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
240 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
243 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
244 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
245 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
246 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
247 <&gcc GCC_PCIE_2B_PIPE_CLK>,
248 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
249 clock-names = "aux", "cfg_ahb", "ref", "rchng",
252 power-domains = <&gcc PCIE_2B_GDSC>;
254 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
255 reset-names = "phy";
257 vdda-phy-supply = <&vreg_l6d>;
258 vdda-pll-supply = <&vreg_l4d>;
260 #clock-cells = <0>;
261 clock-output-names = "pcie_2b_pipe_clk";
263 #phy-cells = <0>;
267 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
270 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
271 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
272 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
273 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
274 <&gcc GCC_PCIE_2A_PIPE_CLK>,
275 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
276 clock-names = "aux", "cfg_ahb", "ref", "rchng",
279 power-domains = <&gcc PCIE_2A_GDSC>;
281 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
282 reset-names = "phy";
284 vdda-phy-supply = <&vreg_l6d>;
285 vdda-pll-supply = <&vreg_l4d>;
287 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
289 #clock-cells = <0>;
290 clock-output-names = "pcie_2a_pipe_clk";
292 #phy-cells = <0>;