Lines Matching +full:pcie +full:- +full:phy +full:- +full:3
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, IPQ8074)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,ipq6018-qmp-pcie-phy
20 - qcom,ipq8074-qmp-gen3-pcie-phy
21 - qcom,ipq8074-qmp-pcie-phy
22 - qcom,ipq9574-qmp-gen3x1-pcie-phy
23 - qcom,ipq9574-qmp-gen3x2-pcie-phy
27 - description: serdes
30 maxItems: 3
32 clock-names:
34 - const: aux
35 - const: cfg_ahb
36 - const: pipe
41 reset-names:
43 - const: phy
44 - const: common
46 "#clock-cells":
49 clock-output-names:
52 "#phy-cells":
56 - compatible
57 - reg
58 - clocks
59 - clock-names
60 - resets
61 - reset-names
62 - "#clock-cells"
63 - clock-output-names
64 - "#phy-cells"
69 - |
70 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
71 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
73 phy@84000 {
74 compatible = "qcom,ipq6018-qmp-pcie-phy";
80 clock-names = "aux",
84 clock-output-names = "gcc_pcie0_pipe_clk_src";
85 #clock-cells = <0>;
87 #phy-cells = <0>;
91 reset-names = "phy",