Lines Matching +full:pipe +full:- +full:grf

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Heiko Stuebner <heiko@sntech.de>
15       - rockchip,rk3562-naneng-combphy
16       - rockchip,rk3568-naneng-combphy
17       - rockchip,rk3576-naneng-combphy
18       - rockchip,rk3588-naneng-combphy
25       - description: reference clock
26       - description: apb clock
27       - description: pipe clock
29   clock-names:
31       - const: ref
32       - const: apb
33       - const: pipe
39   reset-names:
42       - const: phy
43       - const: apb
45   phy-supply:
48   rockchip,enable-ssc:
54   rockchip,ext-refclk:
69   rockchip,pipe-grf:
72       Some additional phy settings are accessed through GRF regs.
74   rockchip,pipe-phy-grf:
77       Some additional pipe settings are accessed through GRF regs.
79   "#phy-cells":
83   - compatible
84   - reg
85   - clocks
86   - clock-names
87   - resets
88   - rockchip,pipe-grf
89   - rockchip,pipe-phy-grf
90   - "#phy-cells"
93   - if:
97             const: rockchip,rk3568-naneng-combphy
102         reset-names:
104   - if:
108             const: rockchip,rk3588-naneng-combphy
113         reset-names:
116         - reset-names
121   - |
122     #include <dt-bindings/clock/rk3568-cru.h>
125       compatible = "rockchip,rk3568-pipe-grf", "syscon";
130       compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
135       compatible = "rockchip,rk3568-naneng-combphy";
140       clock-names = "ref", "apb", "pipe";
141       assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
142       assigned-clock-rates = <100000000>;
144       rockchip,pipe-grf = <&pipegrf>;
145       rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
146       #phy-cells = <1>;