Lines Matching +full:pcie +full:- +full:phy +full:- +full:2
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC Naneng Combo Phy
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-naneng-combphy
16 - rockchip,rk3588-naneng-combphy
23 - description: reference clock
24 - description: apb clock
25 - description: pipe clock
27 clock-names:
29 - const: ref
30 - const: apb
31 - const: pipe
35 maxItems: 2
37 reset-names:
40 - const: phy
41 - const: apb
43 rockchip,enable-ssc:
46 The option SSC can be enabled for U3, SATA and PCIE.
49 rockchip,ext-refclk:
52 Many PCIe connections, especially backplane connections,
56 should be used by both ends of the PCIe link.
57 In PCIe mode one can choose to use an internal or an external reference
59 By default the internal clock is selected. The PCIe PHY provides a 100MHz
62 reference clock needs to be provided to the PCIe PHY.
64 rockchip,pipe-grf:
67 Some additional phy settings are accessed through GRF regs.
69 rockchip,pipe-phy-grf:
74 "#phy-cells":
78 - compatible
79 - reg
80 - clocks
81 - clock-names
82 - resets
83 - rockchip,pipe-grf
84 - rockchip,pipe-phy-grf
85 - "#phy-cells"
88 - if:
92 const: rockchip,rk3568-naneng-combphy
97 reset-names:
99 - if:
103 const: rockchip,rk3588-naneng-combphy
107 minItems: 2
108 reset-names:
109 minItems: 2
111 - reset-names
116 - |
117 #include <dt-bindings/clock/rk3568-cru.h>
120 compatible = "rockchip,rk3568-pipe-grf", "syscon";
125 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
129 combphy0: phy@fe820000 {
130 compatible = "rockchip,rk3568-naneng-combphy";
135 clock-names = "ref", "apb", "pipe";
136 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
137 assigned-clock-rates = <100000000>;
139 rockchip,pipe-grf = <&pipegrf>;
140 rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
141 #phy-cells = <1>;