Lines Matching +full:4 +full:- +full:lane

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14   - Swapnil Jakhade <sjakhade@cadence.com>
15   - Yuti Amonkar <yamonkar@cadence.com>
20       - cdns,sierra-phy-t0
21       - ti,sierra-phy-t0
23   '#address-cells':
26   '#size-cells':
29   '#clock-cells':
35       - description: Sierra PHY reset.
36       - description: Sierra APB reset. This is optional.
38   reset-names:
41       - const: sierra_reset
42       - const: sierra_apb
49   reg-names:
54     maxItems: 4
56   clock-names:
59       - const: cmn_refclk_dig_div
60       - const: cmn_refclk1_dig_div
61       - const: pll0_refclk
62       - const: pll1_refclk
68       configured by hardware. If not present, all sub-node optional properties
72   '^phy@[0-9a-f]$':
75       Each group of PHY lanes with a single master lane should be represented as
76       a sub-node. Note that the actual configuration of each lane is determined
81           The master lane number. This is the lowest numbered lane in the lane group.
87         maxItems: 4
89           Contains list of resets, one per lane, to get all the link lanes out of reset.
91       "#phy-cells":
94       cdns,phy-type:
97           Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
99         enum: [2, 4]
101       cdns,num-lanes:
108       cdns,ssc-mode:
112           Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
118       - reg
119       - resets
120       - "#phy-cells"
125   - compatible
126   - "#address-cells"
127   - "#size-cells"
128   - reg
129   - resets
130   - reset-names
135   - |
136     #include <dt-bindings/phy/phy.h>
139         #address-cells = <2>;
140         #size-cells = <2>;
142         sierra-phy@fd240000 {
143             compatible = "cdns,sierra-phy-t0";
146             reset-names = "sierra_reset", "sierra_apb";
148             clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
149             #address-cells = <1>;
150             #size-cells = <0>;
154                 cdns,num-lanes = <2>;
155                 #phy-cells = <0>;
156                 cdns,phy-type = <PHY_TYPE_PCIE>;
160                 resets = <&phyrst 4>;
161                 cdns,num-lanes = <1>;
162                 #phy-cells = <0>;
163                 cdns,phy-type = <PHY_TYPE_PCIE>;