Lines Matching +full:phy +full:- +full:ref +full:- +full:clk
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek XS-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The XS-PHY controller supports physical layer functionality for USB3.1
18 ----------------------------------
45 pattern: "^xs-phy@[0-9a-f]+$"
49 - enum:
50 - mediatek,mt3611-xsphy
51 - mediatek,mt3612-xsphy
52 - mediatek,mt7988-xsphy
53 - const: mediatek,xsphy
61 "#address-cells":
64 "#size-cells":
69 mediatek,src-ref-clk-mhz:
74 mediatek,src-coef:
77 $ref: /schemas/types.yaml#/definitions/uint32
82 "^usb-phy@[0-9a-f]+$":
85 A sub-node is required for each port the controller provides.
95 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
97 clock-names:
99 - const: ref
101 "#phy-cells":
106 - description: The PHY type
108 - PHY_TYPE_USB2
109 - PHY_TYPE_USB3
112 mediatek,eye-src:
114 The value of slew rate calibrate (U2 phy)
115 $ref: /schemas/types.yaml#/definitions/uint32
119 mediatek,eye-vrt:
121 The selection of VRT reference voltage (U2 phy)
122 $ref: /schemas/types.yaml#/definitions/uint32
126 mediatek,eye-term:
128 The selection of HS_TX TERM reference voltage (U2 phy)
129 $ref: /schemas/types.yaml#/definitions/uint32
133 mediatek,efuse-intr:
135 The selection of Internal Resistor (U2/U3 phy)
136 $ref: /schemas/types.yaml#/definitions/uint32
140 mediatek,efuse-tx-imp:
142 The selection of TX Impedance (U3 phy)
143 $ref: /schemas/types.yaml#/definitions/uint32
147 mediatek,efuse-rx-imp:
149 The selection of RX Impedance (U3 phy)
150 $ref: /schemas/types.yaml#/definitions/uint32
154 mediatek,syscon-type:
155 $ref: /schemas/types.yaml#/definitions/phandle-array
160 - items:
161 - description:
162 Phandle to phy type configuration system controller
163 - description:
164 Phy type configuration register offset
165 - description:
170 - reg
171 - clocks
172 - clock-names
173 - "#phy-cells"
178 - compatible
179 - "#address-cells"
180 - "#size-cells"
181 - ranges
186 - |
187 #include <dt-bindings/phy/phy.h>
189 u3phy: xs-phy@11c40000 {
190 compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
192 mediatek,src-ref-clk-mhz = <26>;
193 mediatek,src-coef = <17>;
194 #address-cells = <1>;
195 #size-cells = <1>;
198 u2port0: usb-phy@11c40000 {
201 clock-names = "ref";
202 mediatek,eye-src = <4>;
203 #phy-cells = <1>;
206 u3port0: usb-phy@11c43000 {
209 clock-names = "ref";
210 mediatek,efuse-intr = <28>;
211 #phy-cells = <1>;