Lines Matching +full:pcie +full:- +full:phy +full:- +full:3
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
37 Version 2/3:
67 pattern: "^t-phy(@[0-9a-f]+)?$"
71 - items:
72 - enum:
73 - mediatek,mt2701-tphy
74 - mediatek,mt7623-tphy
75 - mediatek,mt7622-tphy
76 - mediatek,mt8516-tphy
77 - const: mediatek,generic-tphy-v1
78 - items:
79 - enum:
80 - mediatek,mt2712-tphy
81 - mediatek,mt7629-tphy
82 - mediatek,mt7986-tphy
83 - mediatek,mt8183-tphy
84 - mediatek,mt8186-tphy
85 - mediatek,mt8192-tphy
86 - mediatek,mt8365-tphy
87 - const: mediatek,generic-tphy-v2
88 - items:
89 - enum:
90 - mediatek,mt8188-tphy
91 - mediatek,mt8195-tphy
92 - const: mediatek,generic-tphy-v3
93 - const: mediatek,mt2701-u3phy
95 - const: mediatek,mt2712-u3phy
97 - const: mediatek,mt8173-u3phy
102 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
103 T-PHY V2/V3, such as mt2712.
106 "#address-cells":
109 "#size-cells":
112 # Used with non-empty value if optional 'reg' is not provided.
114 # (child-bus-address, parent-bus-address, length).
117 mediatek,src-ref-clk-mhz:
122 mediatek,src-coef:
130 "^(usb|pcie|sata)-phy@[0-9a-f]+$":
133 A sub-node is required for each port the controller provides.
144 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
145 - description: Reference clock of analog phy
150 clock-names:
153 - const: ref
154 - const: da_ref
156 "#phy-cells":
161 - description: The PHY type
163 - PHY_TYPE_USB2
164 - PHY_TYPE_USB3
165 - PHY_TYPE_PCIE
166 - PHY_TYPE_SATA
167 - PHY_TYPE_SGMII
169 nvmem-cells:
171 - description: internal R efuse for U2 PHY or U3/PCIe PHY
172 - description: rx_imp_sel efuse for U3/PCIe PHY
173 - description: tx_imp_sel efuse for U3/PCIe PHY
176 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these
177 three items should be provided at the same time for U3/PCIe PHY,
179 If unspecified, will use hardware auto-load efuse.
181 nvmem-cell-names:
183 - const: intr
184 - const: rx_imp
185 - const: tx_imp
188 mediatek,eye-src:
190 The value of slew rate calibrate (U2 phy)
195 mediatek,eye-vrt:
197 The selection of VRT reference voltage (U2 phy)
202 mediatek,eye-term:
204 The selection of HS_TX TERM reference voltage (U2 phy)
211 The selection of internal resistor (U2 phy)
218 The selection of disconnect threshold (U2 phy)
223 mediatek,pre-emphasis:
225 The level of pre-emphasis which used to widen the eye opening and
228 8.3% etc. (U2 phy)
231 maximum: 3
238 mediatek,force-mode:
240 The force mode is used to manually switch the shared phy mode between
241 USB3 and PCIe, when USB3 phy type is selected by the consumer, and
242 force-mode is set, will cause phy's power and pipe toggled and force
243 phy as USB3 mode which switched from default PCIe mode. But prefer to
244 use the property "mediatek,syscon-type" for newer SoCs that support it.
247 mediatek,syscon-type:
248 $ref: /schemas/types.yaml#/definitions/phandle-array
252 the field should always be 3 cells long.
255 - description:
257 - description:
259 - description:
261 enum: [0, 1, 2, 3]
264 - reg
265 - "#phy-cells"
270 - compatible
271 - "#address-cells"
272 - "#size-cells"
273 - ranges
278 - |
279 #include <dt-bindings/clock/mt8173-clk.h>
280 #include <dt-bindings/interrupt-controller/arm-gic.h>
281 #include <dt-bindings/interrupt-controller/irq.h>
282 #include <dt-bindings/phy/phy.h>
284 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
286 reg-names = "mac", "ippc";
292 clock-names = "sys_ck";
295 t-phy@11290000 {
296 compatible = "mediatek,mt8173-u3phy";
298 #address-cells = <1>;
299 #size-cells = <1>;
302 u2port0: usb-phy@11290800 {
305 clock-names = "ref", "da_ref";
306 #phy-cells = <1>;
309 u3port0: usb-phy@11290900 {
312 clock-names = "ref";
313 #phy-cells = <1>;
316 u2port1: usb-phy@11291000 {
318 #phy-cells = <1>;