Lines Matching +full:lgm +full:- +full:pcie

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Dilip Kota <eswara.kota@linux.intel.com>
13   Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA
18     pattern: "combophy(@.*|-([0-9]|[1-9][0-9]+))?$"
22       - const: intel,combophy-lgm
23       - const: intel,combo-phy
30       - description: ComboPhy core registers
31       - description: PCIe app core control registers
33   reg-names:
35       - const: core
36       - const: app
41   reset-names:
43       - const: phy
44       - const: core
45       - const: iphy0
46       - const: iphy1
49     $ref: /schemas/types.yaml#/definitions/phandle-array
51       - items:
52           - description: phandle to Chip configuration registers
53           - description: ComboPhy instance id
57     $ref: /schemas/types.yaml#/definitions/phandle-array
59       - items:
60           - description: phandle to HSIO registers
61           - description: ComboPhy instance id
69   intel,phy-mode:
73       See dt-bindings/phy/phy.h for values.
75   "#phy-cells":
79   - compatible
80   - clocks
81   - reg
82   - reg-names
83   - intel,syscfg
84   - intel,hsio
85   - intel,phy-mode
86   - "#phy-cells"
91   - |
92     #include <dt-bindings/phy/phy.h>
94         compatible = "intel,combophy-lgm", "intel,combo-phy";
96         #phy-cells = <1>;
99         reg-names = "core", "app";
104         reset-names = "phy", "core", "iphy0", "iphy1";
107         intel,phy-mode = <PHY_TYPE_PCIE>;