Lines Matching +full:msi +full:- +full:specifier
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: xlnx,nwl-pcie-2.11
22 - description: PCIe bridge registers location.
23 - description: PCIe Controller registers location.
24 - description: PCIe Configuration space region.
26 reg-names:
28 - const: breg
29 - const: pcireg
30 - const: cfg
34 - description: interrupt asserted when miscellaneous interrupt is received
35 - description: unused interrupt(dummy)
36 - description: interrupt asserted when a legacy interrupt is received
37 - description: msi1 interrupt asserted when an MSI is received
38 - description: msi0 interrupt asserted when an MSI is received
40 interrupt-names:
42 - const: misc
43 - const: dummy
44 - const: intx
45 - const: msi1
46 - const: msi0
48 interrupt-map-mask:
50 - const: 0
51 - const: 0
52 - const: 0
53 - const: 7
55 "#interrupt-cells":
58 msi-parent:
59 description: MSI controller the device is capable of using.
61 interrupt-map:
69 power-domains:
75 dma-coherent:
80 description: optional, input clock specifier.
82 legacy-interrupt-controller:
86 "#address-cells":
89 "#interrupt-cells":
92 interrupt-controller: true
95 - "#address-cells"
96 - "#interrupt-cells"
97 - interrupt-controller
102 - compatible
103 - reg
104 - reg-names
105 - interrupts
106 - "#interrupt-cells"
107 - interrupt-map
108 - interrupt-map-mask
109 - msi-controller
110 - power-domains
115 - |
116 #include <dt-bindings/interrupt-controller/arm-gic.h>
117 #include <dt-bindings/interrupt-controller/irq.h>
118 #include <dt-bindings/phy/phy.h>
119 #include <dt-bindings/power/xlnx-zynqmp-power.h>
121 #address-cells = <2>;
122 #size-cells = <2>;
124 compatible = "xlnx,nwl-pcie-2.11";
128 reg-names = "breg", "pcireg", "cfg";
131 #address-cells = <3>;
132 #size-cells = <2>;
133 #interrupt-cells = <1>;
134 msi-controller;
136 interrupt-parent = <&gic>;
140 interrupt-names = "misc", "dummy", "intx", "msi1", "msi0";
141 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
142 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
146 msi-parent = <&nwl_pcie>;
148 power-domains = <&zynqmp_firmware PD_PCIE>;
150 pcie_intc: legacy-interrupt-controller {
151 interrupt-controller;
152 #address-cells = <0>;
153 #interrupt-cells = <1>;