Lines Matching +full:msi +full:- +full:map +full:- +full:mask
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
18 - xlnx,versal-cpm-host-1.00
19 - xlnx,versal-cpm5-host
20 - xlnx,versal-cpm5-host1
24 - description: CPM system level control and status registers.
25 - description: Configuration space region and bridge registers.
26 - description: CPM5 control and status registers.
29 reg-names:
31 - const: cpm_slcr
32 - const: cfg
33 - const: cpm_csr
39 msi-map:
41 Maps a Requester ID to an MSI controller and associated MSI sideband data.
46 "#interrupt-cells":
49 interrupt-controller:
55 "#address-cells":
58 "#interrupt-cells":
61 interrupt-controller: true
64 - reg
65 - reg-names
66 - "#interrupt-cells"
67 - interrupts
68 - interrupt-map
69 - interrupt-map-mask
70 - bus-range
71 - msi-map
72 - interrupt-controller
77 - |
80 #address-cells = <2>;
81 #size-cells = <2>;
83 compatible = "xlnx,versal-cpm-host-1.00";
85 #address-cells = <3>;
86 #interrupt-cells = <1>;
87 #size-cells = <2>;
89 interrupt-parent = <&gic>;
90 interrupt-map-mask = <0 0 0 7>;
91 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
95 bus-range = <0x00 0xff>;
98 msi-map = <0x0 &its_gic 0x0 0x10000>;
101 reg-names = "cpm_slcr", "cfg";
102 pcie_intc_0: interrupt-controller {
103 #address-cells = <0>;
104 #interrupt-cells = <1>;
105 interrupt-controller;
110 compatible = "xlnx,versal-cpm5-host";
112 #address-cells = <3>;
113 #interrupt-cells = <1>;
114 #size-cells = <2>;
116 interrupt-parent = <&gic>;
117 interrupt-map-mask = <0 0 0 7>;
118 interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
122 bus-range = <0x00 0xff>;
125 msi-map = <0x0 &its_gic 0x0 0x10000>;
129 reg-names = "cpm_slcr", "cfg", "cpm_csr";
131 pcie_intc_1: interrupt-controller {
132 #address-cells = <0>;
133 #interrupt-cells = <1>;
134 interrupt-controller;