Lines Matching +full:cdns +full:- +full:pcie +full:- +full:host
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI Host (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - const: ti,j721e-pcie-host
17 - const: ti,j784s4-pcie-host
18 - description: PCIe controller in AM64
20 - const: ti,am64-pcie-host
21 - const: ti,j721e-pcie-host
22 - description: PCIe controller in J7200
24 - const: ti,j7200-pcie-host
25 - const: ti,j721e-pcie-host
26 - description: PCIe controller in J722S
28 - const: ti,j722s-pcie-host
29 - const: ti,j721e-pcie-host
34 reg-names:
36 - const: intd_cfg
37 - const: user_cfg
38 - const: reg
39 - const: cfg
41 ti,syscon-acspcie-proxy-ctrl:
42 $ref: /schemas/types.yaml#/definitions/phandle-array
44 - items:
45 - description: Phandle to the ACSPCIE Proxy Control Register
46 - description: Bitmask corresponding to the PAD IO Buffer
51 ti,syscon-pcie-ctrl:
52 $ref: /schemas/types.yaml#/definitions/phandle-array
54 - items:
55 - description: Phandle to the SYSCON entry
56 - description: pcie_ctrl register offset within SYSCON
57 description: Specifier for configuring PCIe mode and link speed.
59 power-domains:
66 clock-specifier to represent input to the PCIe for 1 item.
69 clock-names:
72 - const: fck
73 - const: pcie_refclk
75 dma-coherent: true
77 vendor-id:
80 device-id:
82 - 0xb00d
83 - 0xb00f
84 - 0xb010
85 - 0xb012
86 - 0xb013
88 msi-map: true
93 interrupt-names:
95 - const: link_state
97 interrupt-controller:
102 interrupt-controller: true
104 '#interrupt-cells':
111 - $ref: cdns-pcie-host.yaml#
112 - if:
116 - ti,am64-pcie-host
119 num-lanes:
122 - if:
126 - ti,j7200-pcie-host
127 - ti,j721e-pcie-host
130 num-lanes:
134 - if:
138 - ti,j784s4-pcie-host
141 num-lanes:
146 - compatible
147 - reg
148 - reg-names
149 - ti,syscon-pcie-ctrl
150 - max-link-speed
151 - num-lanes
152 - power-domains
153 - clocks
154 - clock-names
155 - vendor-id
156 - device-id
157 - msi-map
158 - dma-ranges
159 - ranges
160 - reset-gpios
161 - phys
162 - phy-names
167 - |
168 #include <dt-bindings/soc/ti,sci_pm_domain.h>
169 #include <dt-bindings/gpio/gpio.h>
172 #address-cells = <2>;
173 #size-cells = <2>;
175 pcie0_rc: pcie@2900000 {
176 compatible = "ti,j721e-pcie-host";
181 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
182 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
183 max-link-speed = <3>;
184 num-lanes = <2>;
185 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
187 clock-names = "fck";
189 #address-cells = <3>;
190 #size-cells = <2>;
191 bus-range = <0x0 0xf>;
192 vendor-id = <0x104c>;
193 device-id = <0xb00d>;
194 msi-map = <0x0 &gic_its 0x0 0x10000>;
195 dma-coherent;
196 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
198 phy-names = "pcie-phy";
201 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;