Lines Matching +full:rk3568 +full:- +full:pcie

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe Root Complex controller on Rockchip SoCs
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
15 RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
16 PCIe IP and thus inherits all the common properties defined in
17 snps,dw-pcie.yaml.
20 - $ref: /schemas/pci/snps,dw-pcie.yaml#
21 - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
26 - const: rockchip,rk3568-pcie
27 - items:
28 - enum:
29 - rockchip,rk3588-pcie
30 - const: rockchip,rk3568-pcie
34 - description: Data Bus Interface (DBI) registers
35 - description: Rockchip designed configuration registers
36 - description: Config registers
38 reg-names:
40 - const: dbi
41 - const: apb
42 - const: config
44 legacy-interrupt-controller:
49 "#address-cells":
52 "#interrupt-cells":
55 interrupt-controller: true
59 - description: combined legacy interrupt
61 - "#address-cells"
62 - "#interrupt-cells"
63 - interrupt-controller
64 - interrupts
66 msi-map: true
72 vpcie3v3-supply: true
75 - msi-map
80 - |
81 #include <dt-bindings/interrupt-controller/arm-gic.h>
84 #address-cells = <2>;
85 #size-cells = <2>;
87 pcie3x2: pcie@fe280000 {
88 compatible = "rockchip,rk3568-pcie";
92 reg-names = "dbi", "apb", "config";
93 bus-range = <0x20 0x2f>;
97 clock-names = "aclk_mst", "aclk_slv",
106 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
107 linux,pci-domain = <2>;
108 max-link-speed = <2>;
109 msi-map = <0x2000 &its 0x2000 0x1000>;
110 num-lanes = <2>;
112 phy-names = "pcie-phy";
113 power-domains = <&power 15>;
117 reset-names = "pipe";
118 #address-cells = <3>;
119 #size-cells = <2>;
121 legacy-interrupt-controller {
122 interrupt-controller;
123 #address-cells = <0>;
124 #interrupt-cells = <1>;
125 interrupt-parent = <&gic>;