Lines Matching +full:rk3568 +full:- +full:pcie
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare based PCIe Endpoint controller on Rockchip SoCs
10 - Niklas Cassel <cassel@kernel.org>
13 RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare
14 PCIe IP and thus inherits all the common properties defined in
15 snps,dw-pcie-ep.yaml.
18 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
19 - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
24 - rockchip,rk3568-pcie-ep
25 - rockchip,rk3588-pcie-ep
29 - description: Data Bus Interface (DBI) registers
30 - description: Data Bus Interface (DBI) shadow registers
31 - description: Rockchip designed configuration registers
32 - description: Memory region used to map remote RC address space
33 - description: Internal Address Translation Unit (iATU) registers
35 reg-names:
37 - const: dbi
38 - const: dbi2
39 - const: apb
40 - const: addr_space
41 - const: atu
44 - interrupts
45 - interrupt-names
50 - |
51 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
52 #include <dt-bindings/interrupt-controller/arm-gic.h>
53 #include <dt-bindings/interrupt-controller/irq.h>
54 #include <dt-bindings/power/rk3588-power.h>
55 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
58 #address-cells = <2>;
59 #size-cells = <2>;
61 pcie3x4_ep: pcie-ep@fe150000 {
62 compatible = "rockchip,rk3588-pcie-ep";
68 reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
72 clock-names = "aclk_mst", "aclk_slv",
84 interrupt-names = "sys", "pmc", "msg", "legacy", "err",
86 max-link-speed = <3>;
87 num-lanes = <4>;
89 phy-names = "pcie-phy";
90 power-domains = <&power RK3588_PD_PCIE>;
92 reset-names = "pwr", "pipe";