Lines Matching +full:pcie +full:- +full:phy +full:- +full:3

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip AXI PCIe Endpoint
10   - Shawn Lin <shawn.lin@rock-chips.com>
13   - $ref: /schemas/pci/pci-ep.yaml#
14   - $ref: rockchip,rk3399-pcie-common.yaml#
18     const: rockchip,rk3399-pcie-ep
22   reg-names:
24       - const: apb-base
25       - const: mem-base
27   rockchip,max-outbound-regions:
34   - rockchip,max-outbound-regions
39   - |
40     #include <dt-bindings/interrupt-controller/arm-gic.h>
41     #include <dt-bindings/gpio/gpio.h>
42     #include <dt-bindings/clock/rk3399-cru.h>
45         #address-cells = <2>;
46         #size-cells = <2>;
48         pcie-ep@f8000000 {
49             compatible = "rockchip,rk3399-pcie-ep";
51             reg-names = "apb-base", "mem-base";
54             clock-names = "aclk", "aclk-perf",
56             max-functions = /bits/ 8 <8>;
57             num-lanes = <4>;
61             reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
63             phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
64             phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
65             rockchip,max-outbound-regions = <16>;
66             pinctrl-names = "default";
67             pinctrl-0 = <&pcie_clkreqnb_cpm>;