Lines Matching +full:r8a779f0 +full:- +full:pcie
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Renesas Electronics Corp.
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Gen4 PCIe Host
11 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
14 - $ref: snps,dw-pcie.yaml#
19 - enum:
20 - renesas,r8a779f0-pcie # R-Car S4-8
21 - renesas,r8a779g0-pcie # R-Car V4H
22 - renesas,r8a779h0-pcie # R-Car V4M
23 - const: renesas,rcar-gen4-pcie # R-Car Gen4
28 reg-names:
30 - const: dbi
31 - const: dbi2
32 - const: atu
33 - const: dma
34 - const: app
35 - const: phy
36 - const: config
41 interrupt-names:
43 - const: msi
44 - const: dma
45 - const: sft_ce
46 - const: app
51 clock-names:
53 - const: core
54 - const: ref
56 power-domains:
62 reset-names:
64 - const: pwr
66 max-link-speed:
69 num-lanes:
73 - compatible
74 - reg
75 - reg-names
76 - interrupts
77 - interrupt-names
78 - clocks
79 - clock-names
80 - power-domains
81 - resets
82 - reset-names
87 - |
88 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
89 #include <dt-bindings/interrupt-controller/arm-gic.h>
90 #include <dt-bindings/power/r8a779f0-sysc.h>
93 #address-cells = <2>;
94 #size-cells = <2>;
96 pcie: pcie@e65d0000 {
97 compatible = "renesas,r8a779f0-pcie", "renesas,rcar-gen4-pcie";
102 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
107 interrupt-names = "msi", "dma", "sft_ce", "app";
109 clock-names = "core", "ref";
110 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
112 reset-names = "pwr";
113 max-link-speed = <4>;
114 num-lanes = <2>;
115 #address-cells = <3>;
116 #size-cells = <2>;
117 bus-range = <0x00 0xff>;
121 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
122 #interrupt-cells = <1>;
123 interrupt-map-mask = <0 0 0 7>;
124 interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
128 snps,enable-cdm-check;