Lines Matching +full:axi +full:- +full:config
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - const: qcom,pcie-sm8550
21 - items:
22 - enum:
23 - qcom,pcie-sm8650
24 - const: qcom,pcie-sm8550
30 reg-names:
33 - const: parf # Qualcomm specific registers
34 - const: dbi # DesignWare PCIe registers
35 - const: elbi # External local bus interface registers
36 - const: atu # ATU address space
37 - const: config # PCIe configuration space
38 - const: mhi # MHI registers
44 clock-names:
47 - const: aux # Auxiliary clock
48 - const: cfg # Configuration clock
49 - const: bus_master # Master AXI clock
50 - const: bus_slave # Slave AXI clock
51 - const: slave_q2a # Slave Q2A clock
52 - const: ddrss_sf_tbu # PCIe SF TBU clock
53 - const: noc_aggr # Aggre NoC PCIe AXI clock
54 - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
60 interrupt-names:
62 - const: msi0
63 - const: msi1
64 - const: msi2
65 - const: msi3
66 - const: msi4
67 - const: msi5
68 - const: msi6
69 - const: msi7
75 reset-names:
78 - const: pci # PCIe core reset
79 - const: link_down # PCIe link down reset
82 - $ref: qcom,pcie-common.yaml#
87 - |
88 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
89 #include <dt-bindings/gpio/gpio.h>
90 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
91 #include <dt-bindings/interrupt-controller/arm-gic.h>
94 #address-cells = <2>;
95 #size-cells = <2>;
98 compatible = "qcom,pcie-sm8550";
104 reg-names = "parf", "dbi", "elbi", "atu", "config";
108 bus-range = <0x00 0xff>;
110 linux,pci-domain = <0>;
111 num-lanes = <2>;
113 #address-cells = <3>;
114 #size-cells = <2>;
123 clock-names = "aux",
131 dma-coherent;
141 interrupt-names = "msi0", "msi1", "msi2", "msi3",
143 #interrupt-cells = <1>;
144 interrupt-map-mask = <0 0 0 0x7>;
145 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
152 interconnect-names = "pcie-mem", "cpu-pcie";
154 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
158 phy-names = "pciephy";
160 pinctrl-0 = <&pcie0_default_state>;
161 pinctrl-names = "default";
163 power-domains = <&gcc PCIE_0_GDSC>;
166 reset-names = "pci";
168 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
169 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;