Lines Matching +full:axi +full:- +full:config
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 const: qcom,pcie-sm8250
25 reg-names:
28 - const: parf # Qualcomm specific registers
29 - const: dbi # DesignWare PCIe registers
30 - const: elbi # External local bus interface registers
31 - const: atu # ATU address space
32 - const: config # PCIe configuration space
33 - const: mhi # MHI registers
39 clock-names:
42 - items:
43 - const: pipe # PIPE clock
44 - const: aux # Auxiliary clock
45 - const: cfg # Configuration clock
46 - const: bus_master # Master AXI clock
47 - const: bus_slave # Slave AXI clock
48 - const: slave_q2a # Slave Q2A clock
49 - const: ref # REFERENCE clock
50 - const: tbu # PCIe TBU clock
51 - const: ddrss_sf_tbu # PCIe SF TBU clock
52 - items:
53 - const: pipe # PIPE clock
54 - const: aux # Auxiliary clock
55 - const: cfg # Configuration clock
56 - const: bus_master # Master AXI clock
57 - const: bus_slave # Slave AXI clock
58 - const: slave_q2a # Slave Q2A clock
59 - const: tbu # PCIe TBU clock
60 - const: ddrss_sf_tbu # PCIe SF TBU clock
66 interrupt-names:
68 - const: msi0
69 - const: msi1
70 - const: msi2
71 - const: msi3
72 - const: msi4
73 - const: msi5
74 - const: msi6
75 - const: msi7
80 reset-names:
82 - const: pci
85 - $ref: qcom,pcie-common.yaml#
90 - |
91 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
92 #include <dt-bindings/gpio/gpio.h>
93 #include <dt-bindings/interconnect/qcom,sm8250.h>
94 #include <dt-bindings/interrupt-controller/arm-gic.h>
97 #address-cells = <2>;
98 #size-cells = <2>;
101 compatible = "qcom,pcie-sm8250";
108 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
112 bus-range = <0x00 0xff>;
114 linux,pci-domain = <0>;
115 num-lanes = <1>;
117 #address-cells = <3>;
118 #size-cells = <2>;
128 clock-names = "pipe",
137 dma-coherent;
147 interrupt-names = "msi0", "msi1", "msi2", "msi3",
149 #interrupt-cells = <1>;
150 interrupt-map-mask = <0 0 0 0x7>;
151 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
156 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
160 phy-names = "pciephy";
162 pinctrl-0 = <&pcie0_default_state>;
163 pinctrl-names = "default";
165 power-domains = <&gcc PCIE_0_GDSC>;
168 reset-names = "pci";
170 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
171 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;