Lines Matching +full:rpmh +full:- +full:based
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys
19 const: qcom,pcie-sm8150
25 reg-names:
28 - const: parf # Qualcomm specific registers
29 - const: dbi # DesignWare PCIe registers
30 - const: elbi # External local bus interface registers
31 - const: atu # ATU address space
32 - const: config # PCIe configuration space
33 - const: mhi # MHI registers
39 clock-names:
41 - const: pipe # PIPE clock
42 - const: aux # Auxiliary clock
43 - const: cfg # Configuration clock
44 - const: bus_master # Master AXI clock
45 - const: bus_slave # Slave AXI clock
46 - const: slave_q2a # Slave Q2A clock
47 - const: tbu # PCIe TBU clock
48 - const: ref # REFERENCE clock
54 interrupt-names:
56 - const: msi0
57 - const: msi1
58 - const: msi2
59 - const: msi3
60 - const: msi4
61 - const: msi5
62 - const: msi6
63 - const: msi7
68 reset-names:
70 - const: pci
73 - $ref: qcom,pcie-common.yaml#
78 - |
79 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
80 #include <dt-bindings/clock/qcom,rpmh.h>
81 #include <dt-bindings/gpio/gpio.h>
82 #include <dt-bindings/interconnect/qcom,sm8150.h>
83 #include <dt-bindings/interrupt-controller/arm-gic.h>
86 #address-cells = <2>;
87 #size-cells = <2>;
89 compatible = "qcom,pcie-sm8150";
95 reg-names = "parf", "dbi", "elbi", "atu", "config";
99 bus-range = <0x00 0xff>;
101 linux,pci-domain = <0>;
102 num-lanes = <1>;
104 #address-cells = <3>;
105 #size-cells = <2>;
115 clock-names = "pipe",
132 interrupt-names = "msi0", "msi1", "msi2", "msi3",
134 #interrupt-cells = <1>;
135 interrupt-map-mask = <0 0 0 0x7>;
136 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
141 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
145 phy-names = "pciephy";
147 pinctrl-0 = <&pcie0_default_state>;
148 pinctrl-names = "default";
150 power-domains = <&gcc PCIE_0_GDSC>;
153 reset-names = "pci";
155 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
156 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;