Lines Matching +full:gcc +full:- +full:sc8280xp
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC8280XP PCI Express Root Complex
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys
20 - qcom,pcie-sa8540p
21 - qcom,pcie-sc8280xp
27 reg-names:
30 - const: parf # Qualcomm specific registers
31 - const: dbi # DesignWare PCIe registers
32 - const: elbi # External local bus interface registers
33 - const: atu # ATU address space
34 - const: config # PCIe configuration space
35 - const: mhi # MHI registers
41 clock-names:
44 - const: aux # Auxiliary clock
45 - const: cfg # Configuration clock
46 - const: bus_master # Master AXI clock
47 - const: bus_slave # Slave AXI clock
48 - const: slave_q2a # Slave Q2A clock
49 - const: ddrss_sf_tbu # PCIe SF TBU clock
50 - const: noc_aggr_4 # NoC aggregate 4 clock
51 - const: noc_aggr_south_sf # NoC aggregate South SF clock
52 - const: cnoc_qx # Configuration NoC QX clock
57 reset-names:
59 - const: pci
62 - interconnects
63 - interconnect-names
66 - $ref: qcom,pcie-common.yaml#
67 - if:
72 - qcom,pcie-sc8280xp
78 interrupt-names:
80 - const: msi0
81 - const: msi1
82 - const: msi2
83 - const: msi3
88 interrupt-names:
90 - const: msi
95 - |
96 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
97 #include <dt-bindings/gpio/gpio.h>
98 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
99 #include <dt-bindings/interrupt-controller/arm-gic.h>
102 #address-cells = <2>;
103 #size-cells = <2>;
106 compatible = "qcom,pcie-sc8280xp";
113 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
117 bus-range = <0x00 0xff>;
119 linux,pci-domain = <2>;
120 num-lanes = <4>;
122 #address-cells = <3>;
123 #size-cells = <2>;
125 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
126 assigned-clock-rates = <19200000>;
127 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
128 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
129 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
130 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
131 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
132 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
133 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
134 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
135 clock-names = "aux",
144 dma-coherent;
150 interrupt-names = "msi0", "msi1", "msi2", "msi3";
151 #interrupt-cells = <1>;
152 interrupt-map-mask = <0 0 0 0x7>;
153 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
160 interconnect-names = "pcie-mem", "cpu-pcie";
163 phy-names = "pciephy";
165 pinctrl-0 = <&pcie2a_default>;
166 pinctrl-names = "default";
168 power-domains = <&gcc PCIE_2A_GDSC>;
170 resets = <&gcc GCC_PCIE_2A_BCR>;
171 reset-names = "pci";
173 perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
174 wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
175 vddpe-3v3-supply = <&vreg_nvme>;