Lines Matching +full:sa8775p +full:- +full:gcc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SA8775p PCI Express Root Complex
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys
20 - const: qcom,pcie-sa8775p
21 - items:
22 - enum:
23 - qcom,pcie-qcs8300
24 - const: qcom,pcie-sa8775p
30 reg-names:
32 - const: parf # Qualcomm specific registers
33 - const: dbi # DesignWare PCIe registers
34 - const: elbi # External local bus interface registers
35 - const: atu # ATU address space
36 - const: config # PCIe configuration space
37 - const: mhi # MHI registers
43 clock-names:
45 - const: aux # Auxiliary clock
46 - const: cfg # Configuration clock
47 - const: bus_master # Master AXI clock
48 - const: bus_slave # Slave AXI clock
49 - const: slave_q2a # Slave Q2A clock
55 interrupt-names:
58 - const: msi0
59 - const: msi1
60 - const: msi2
61 - const: msi3
62 - const: msi4
63 - const: msi5
64 - const: msi6
65 - const: msi7
66 - const: global
70 - description: PCIe controller reset
71 - description: PCIe link down reset
73 reset-names:
75 - const: pci
76 - const: link_down
79 - interconnects
80 - interconnect-names
83 - $ref: qcom,pcie-common.yaml#
88 - |
89 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
90 #include <dt-bindings/clock/qcom,rpmh.h>
91 #include <dt-bindings/gpio/gpio.h>
92 #include <dt-bindings/interrupt-controller/arm-gic.h>
93 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
96 #address-cells = <2>;
97 #size-cells = <2>;
100 compatible = "qcom,pcie-sa8775p";
107 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
111 bus-range = <0x00 0xff>;
113 linux,pci-domain = <0>;
114 num-lanes = <2>;
116 #address-cells = <3>;
117 #size-cells = <2>;
119 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
120 assigned-clock-rates = <19200000>;
122 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
123 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
124 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
125 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
126 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
127 clock-names = "aux",
133 dma-coherent;
144 interrupt-names = "msi0",
153 #interrupt-cells = <1>;
154 interrupt-map-mask = <0 0 0 0x7>;
155 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
162 interconnect-names = "pcie-mem", "cpu-pcie";
164 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
168 phy-names = "pciephy";
170 power-domains = <&gcc PCIE_0_GDSC>;
172 resets = <&gcc GCC_PCIE_0_BCR>,
173 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
174 reset-names = "pci",
177 perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
178 wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;