Lines Matching +full:rpmh +full:- +full:based
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys
19 const: qcom,pcie-sa8775p
25 reg-names:
27 - const: parf # Qualcomm specific registers
28 - const: dbi # DesignWare PCIe registers
29 - const: elbi # External local bus interface registers
30 - const: atu # ATU address space
31 - const: config # PCIe configuration space
32 - const: mhi # MHI registers
38 clock-names:
40 - const: aux # Auxiliary clock
41 - const: cfg # Configuration clock
42 - const: bus_master # Master AXI clock
43 - const: bus_slave # Slave AXI clock
44 - const: slave_q2a # Slave Q2A clock
50 interrupt-names:
52 - const: msi0
53 - const: msi1
54 - const: msi2
55 - const: msi3
56 - const: msi4
57 - const: msi5
58 - const: msi6
59 - const: msi7
64 reset-names:
66 - const: pci
69 - interconnects
70 - interconnect-names
73 - $ref: qcom,pcie-common.yaml#
78 - |
79 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
80 #include <dt-bindings/clock/qcom,rpmh.h>
81 #include <dt-bindings/gpio/gpio.h>
82 #include <dt-bindings/interrupt-controller/arm-gic.h>
83 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
86 #address-cells = <2>;
87 #size-cells = <2>;
90 compatible = "qcom,pcie-sa8775p";
97 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
101 bus-range = <0x00 0xff>;
103 linux,pci-domain = <0>;
104 num-lanes = <2>;
106 #address-cells = <3>;
107 #size-cells = <2>;
109 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
110 assigned-clock-rates = <19200000>;
117 clock-names = "aux",
123 dma-coherent;
133 interrupt-names = "msi0",
141 #interrupt-cells = <1>;
142 interrupt-map-mask = <0 0 0 0x7>;
143 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
150 interconnect-names = "pcie-mem", "cpu-pcie";
152 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
156 phy-names = "pciephy";
158 power-domains = <&gcc PCIE_0_GDSC>;
161 reset-names = "pci";
163 perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
164 wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;