Lines Matching +full:non +full:- +full:prefetchable
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sa8255p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 const: qcom,pcie-sa8255p
25 address corresponds to the first bus in the "bus-range" property. If
26 no "bus-range" is specified, this will be bus 0 (the default).
31 As described in IEEE Std 1275-1994, but must provide at least a
32 definition of non-prefetchable memory. One or both of prefetchable Memory
41 interrupt-names:
43 - const: msi0
44 - const: msi1
45 - const: msi2
46 - const: msi3
47 - const: msi4
48 - const: msi5
49 - const: msi6
50 - const: msi7
52 power-domains:
55 dma-coherent: true
56 iommu-map: true
59 - compatible
60 - reg
61 - ranges
62 - power-domains
63 - interrupts
64 - interrupt-names
67 - $ref: /schemas/pci/pci-host-bridge.yaml#
72 - |
73 #include <dt-bindings/interrupt-controller/arm-gic.h>
76 #address-cells = <2>;
77 #size-cells = <2>;
80 compatible = "qcom,pcie-sa8255p";
83 #address-cells = <3>;
84 #size-cells = <2>;
87 bus-range = <0x00 0xff>;
88 dma-coherent;
89 linux,pci-domain = <0>;
90 power-domains = <&scmi5_pd 0>;
91 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
93 interrupt-parent = <&intc>;
102 interrupt-names = "msi0", "msi1", "msi2", "msi3",
105 #interrupt-cells = <1>;
106 interrupt-map-mask = <0 0 0 0x7>;
107 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
115 bus-range = <0x01 0xff>;
117 #address-cells = <3>;
118 #size-cells = <2>;