Lines Matching +full:0 +full:x88000
23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
99 bus-range = <0x00 0xff>;
103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
105 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
106 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
107 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
108 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
109 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
110 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
111 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
112 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
113 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
114 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
115 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
116 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
117 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
118 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
119 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
120 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
122 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
123 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
124 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
125 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
126 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
127 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
128 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
129 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
131 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
132 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
134 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
135 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
137 pcie@1,0 {
139 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
140 reg = <0x0800 0 0 0 0>;
144 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
145 0x81000000 0 0 0x81000000 0x1 0 1 0>;
146 interrupt-map-mask = <0 0 0 0>;
147 interrupt-map = <0 0 0 0 &mpic 58>;
148 marvell,pcie-port = <0>;
149 marvell,pcie-lane = <0>;
158 pcie@2,0 {
160 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
161 reg = <0x1000 0 0 0 0>;
165 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
166 0x81000000 0 0 0x81000000 0x2 0 1 0>;
167 interrupt-map-mask = <0 0 0 0>;
168 interrupt-map = <0 0 0 0 &mpic 59>;
169 marvell,pcie-port = <0>;
175 pcie@3,0 {
177 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
178 reg = <0x1800 0 0 0 0>;
182 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
183 0x81000000 0 0 0x81000000 0x3 0 1 0>;
184 interrupt-map-mask = <0 0 0 0>;
185 interrupt-map = <0 0 0 0 &mpic 60>;
186 marvell,pcie-port = <0>;
192 pcie@4,0 {
194 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
195 reg = <0x2000 0 0 0 0>;
199 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
200 0x81000000 0 0 0x81000000 0x4 0 1 0>;
201 interrupt-map-mask = <0 0 0 0>;
202 interrupt-map = <0 0 0 0 &mpic 61>;
203 marvell,pcie-port = <0>;
209 pcie@5,0 {
211 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
212 reg = <0x2800 0 0 0 0>;
216 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
217 0x81000000 0 0 0x81000000 0x5 0 1 0>;
218 interrupt-map-mask = <0 0 0 0>;
219 interrupt-map = <0 0 0 0 &mpic 62>;
221 marvell,pcie-lane = <0>;
226 pcie@6,0 {
228 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
229 reg = <0x3000 0 0 0 0>;
233 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
234 0x81000000 0 0 0x81000000 0x6 0 1 0>;
235 interrupt-map-mask = <0 0 0 0>;
236 interrupt-map = <0 0 0 0 &mpic 63>;
243 pcie@7,0 {
245 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
246 reg = <0x3800 0 0 0 0>;
250 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
251 0x81000000 0 0 0x81000000 0x7 0 1 0>;
252 interrupt-map-mask = <0 0 0 0>;
253 interrupt-map = <0 0 0 0 &mpic 64>;
260 pcie@8,0 {
262 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
263 reg = <0x4000 0 0 0 0>;
267 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
268 0x81000000 0 0 0x81000000 0x8 0 1 0>;
269 interrupt-map-mask = <0 0 0 0>;
270 interrupt-map = <0 0 0 0 &mpic 65>;
277 pcie@9,0 {
279 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
280 reg = <0x4800 0 0 0 0>;
284 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
285 0x81000000 0 0 0x81000000 0x9 0 1 0>;
286 interrupt-map-mask = <0 0 0 0>;
287 interrupt-map = <0 0 0 0 &mpic 99>;
289 marvell,pcie-lane = <0>;
294 pcie@a,0 {
296 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
297 reg = <0x5000 0 0 0 0>;
301 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
302 0x81000000 0 0 0x81000000 0xa 0 1 0>;
303 interrupt-map-mask = <0 0 0 0>;
304 interrupt-map = <0 0 0 0 &mpic 103>;
306 marvell,pcie-lane = <0>;