Lines Matching +full:pcie +full:- +full:phy +full:- +full:3
1 MediaTek Gen2 PCIe controller
4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
11 - device_type: Must be "pci"
12 - reg: Base addresses and lengths of the root ports.
13 - reg-names: Names of the above areas to use during resource lookup.
14 - #address-cells: Address representation for root ports (must be 3)
15 - #size-cells: Size representation for root ports (must be 2)
16 - clocks: Must contain an entry for each entry in clock-names.
17 See ../clocks/clock-bindings.txt for details.
18 - clock-names:
20 - sys_ckN :transaction layer and data link layer clock
22 - free_ck :for reference clock of PCIe subsys
24 - ahb_ckN :AHB slave interface operating clock for CSR access and RC
27 - axi_ckN :application layer MMIO channel operating clock
28 - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
30 - obff_ckN :OBFF functional block operating clock
31 - pipe_ckN :LTSSM and PHY/MAC layer operating clock
33 - phys: List of PHY specifiers (used by generic PHY framework).
34 - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
36 - power-domains: A phandle and power domain specifier pair to the power domain
38 - bus-range: Range of bus numbers associated with this controller.
39 - ranges: Ranges for the PCI memory and I/O regions.
42 - #interrupt-cells: Size representation for interrupts (must be 1)
43 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
46 - resets: Must contain an entry for each entry in reset-names.
48 - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
52 -interrupts: A list of interrupt outputs of the controller, must have one
53 entry for each PCIe port
54 - interrupt-names: Must include the following entries:
55 - "pcie_irq": The interrupt that is asserted when an MSI/INTX is received
56 - linux,pci-domain: PCI domain ID. Should be unique for each host controller
58 In addition, the device tree node must have sub-nodes describing each
59 PCIe port interface, having the following mandatory properties:
62 - device_type: Must be "pci"
63 - reg: Only the first four bytes are used to refer to the correct bus number
65 - #address-cells: Must be 3
66 - #size-cells: Must be 2
67 - #interrupt-cells: Must be 1
68 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
71 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
77 compatible = "mediatek,mt7623-hifsys",
78 "mediatek,mt2701-hifsys",
81 #clock-cells = <1>;
82 #reset-cells = <1>;
85 pcie: pcie@1a140000 {
86 compatible = "mediatek,mt7623-pcie";
88 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
92 reg-names = "subsys", "port0", "port1", "port2";
93 #address-cells = <3>;
94 #size-cells = <2>;
95 #interrupt-cells = <1>;
96 interrupt-map-mask = <0xf800 0 0 0>;
97 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
104 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
108 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
111 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
112 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
113 bus-range = <0x00 0xff>;
117 pcie@0,0 {
119 #address-cells = <3>;
120 #size-cells = <2>;
121 #interrupt-cells = <1>;
122 interrupt-map-mask = <0 0 0 0>;
123 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
127 pcie@1,0 {
129 #address-cells = <3>;
130 #size-cells = <2>;
131 #interrupt-cells = <1>;
132 interrupt-map-mask = <0 0 0 0>;
133 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
137 pcie@2,0 {
139 #address-cells = <3>;
140 #size-cells = <2>;
141 #interrupt-cells = <1>;
142 interrupt-map-mask = <0 0 0 0>;
143 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
150 pcie1: pcie@112ff000 {
151 compatible = "mediatek,mt2712-pcie";
154 reg-names = "port1";
155 linux,pci-domain = <1>;
156 #address-cells = <3>;
157 #size-cells = <2>;
159 interrupt-names = "pcie_irq";
162 clock-names = "sys_ck1", "ahb_ck1";
164 phy-names = "pcie-phy1";
165 bus-range = <0x00 0xff>;
169 #interrupt-cells = <1>;
170 interrupt-map-mask = <0 0 0 7>;
171 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
173 <0 0 0 3 &pcie_intc1 2>,
174 <0 0 0 4 &pcie_intc1 3>;
175 pcie_intc1: interrupt-controller {
176 interrupt-controller;
177 #address-cells = <0>;
178 #interrupt-cells = <1>;
182 pcie0: pcie@11700000 {
183 compatible = "mediatek,mt2712-pcie";
186 reg-names = "port0";
187 linux,pci-domain = <0>;
188 #address-cells = <3>;
189 #size-cells = <2>;
191 interrupt-names = "pcie_irq";
194 clock-names = "sys_ck0", "ahb_ck0";
196 phy-names = "pcie-phy0";
197 bus-range = <0x00 0xff>;
201 #interrupt-cells = <1>;
202 interrupt-map-mask = <0 0 0 7>;
203 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
205 <0 0 0 3 &pcie_intc0 2>,
206 <0 0 0 4 &pcie_intc0 3>;
207 pcie_intc0: interrupt-controller {
208 interrupt-controller;
209 #address-cells = <0>;
210 #interrupt-cells = <1>;
216 pcie0: pcie@1a143000 {
217 compatible = "mediatek,mt7622-pcie";
220 reg-names = "port0";
221 linux,pci-domain = <0>;
222 #address-cells = <3>;
223 #size-cells = <2>;
225 interrupt-names = "pcie_irq";
232 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
235 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
236 bus-range = <0x00 0xff>;
240 #interrupt-cells = <1>;
241 interrupt-map-mask = <0 0 0 7>;
242 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
244 <0 0 0 3 &pcie_intc0 2>,
245 <0 0 0 4 &pcie_intc0 3>;
246 pcie_intc0: interrupt-controller {
247 interrupt-controller;
248 #address-cells = <0>;
249 #interrupt-cells = <1>;
253 pcie1: pcie@1a145000 {
254 compatible = "mediatek,mt7622-pcie";
257 reg-names = "port1";
258 linux,pci-domain = <1>;
259 #address-cells = <3>;
260 #size-cells = <2>;
262 interrupt-names = "pcie_irq";
270 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
273 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
274 bus-range = <0x00 0xff>;
278 #interrupt-cells = <1>;
279 interrupt-map-mask = <0 0 0 7>;
280 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
282 <0 0 0 3 &pcie_intc1 2>,
283 <0 0 0 4 &pcie_intc1 3>;
284 pcie_intc1: interrupt-controller {
285 interrupt-controller;
286 #address-cells = <0>;
287 #interrupt-cells = <1>;