Lines Matching +full:pcie +full:- +full:phy +full:- +full:1
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Gen3 PCIe controller on MediaTek SoCs
10 - Jianjun Wang <jianjun.wang@mediatek.com>
13 PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
19 +-----+
21 +-----+
24 port->irq
26 +-+-+-+-+-+-+-+-+
27 |0|1|2|3|4|5|6|7| (PCIe intc)
28 +-+-+-+-+-+-+-+-+
31 +-------+ +------+ +-----------+
33 +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
34 |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)
35 +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
49 - items:
50 - enum:
51 - mediatek,mt7986-pcie
52 - mediatek,mt8188-pcie
53 - mediatek,mt8195-pcie
54 - const: mediatek,mt8192-pcie
55 - const: mediatek,mt8192-pcie
56 - const: airoha,en7581-pcie
59 maxItems: 1
61 reg-names:
63 - const: pcie-mac
66 maxItems: 1
69 minItems: 1
72 iommu-map:
73 maxItems: 1
75 iommu-map-mask:
79 minItems: 1
82 reset-names:
83 minItems: 1
86 enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
89 minItems: 1
92 clock-names:
93 minItems: 1
96 assigned-clocks:
97 maxItems: 1
99 assigned-clock-parents:
100 maxItems: 1
103 maxItems: 1
105 phy-names:
107 - const: pcie-phy
109 power-domains:
110 maxItems: 1
112 '#interrupt-cells':
113 const: 1
115 interrupt-controller:
119 '#address-cells':
121 '#interrupt-cells':
122 const: 1
123 interrupt-controller: true
126 - '#address-cells'
127 - '#interrupt-cells'
128 - interrupt-controller
133 - compatible
134 - reg
135 - reg-names
136 - interrupts
137 - ranges
138 - clocks
139 - clock-names
140 - '#interrupt-cells'
141 - interrupt-controller
144 - $ref: /schemas/pci/pci-host-bridge.yaml#
145 - if:
148 const: mediatek,mt8192-pcie
154 clock-names:
156 - const: pl_250m
157 - const: tl_26m
158 - const: tl_96m
159 - const: tl_32k
160 - const: peri_26m
161 - const: top_133m
164 minItems: 1
167 reset-names:
168 minItems: 1
171 - if:
176 - mediatek,mt8188-pcie
177 - mediatek,mt8195-pcie
183 clock-names:
185 - const: pl_250m
186 - const: tl_26m
187 - const: tl_96m
188 - const: tl_32k
189 - const: peri_26m
190 - const: peri_mem
193 minItems: 1
196 reset-names:
197 minItems: 1
200 - if:
205 - mediatek,mt7986-pcie
211 clock-names:
213 - const: pl_250m
214 - const: tl_26m
215 - const: peri_26m
216 - const: top_133m
219 minItems: 1
222 reset-names:
223 minItems: 1
226 - if:
229 const: airoha,en7581-pcie
233 maxItems: 1
235 clock-names:
237 - const: sys-ck
242 reset-names:
244 - const: phy-lane0
245 - const: phy-lane1
246 - const: phy-lane2
251 - |
252 #include <dt-bindings/interrupt-controller/arm-gic.h>
253 #include <dt-bindings/interrupt-controller/irq.h>
256 #address-cells = <2>;
257 #size-cells = <2>;
259 pcie: pcie@11230000 {
260 compatible = "mediatek,mt8192-pcie";
262 #address-cells = <3>;
263 #size-cells = <2>;
265 reg-names = "pcie-mac";
267 bus-range = <0x00 0xff>;
276 clock-names = "pl_250m", "tl_26m", "tl_96m",
278 assigned-clocks = <&topckgen 50>;
279 assigned-clock-parents = <&topckgen 91>;
282 phy-names = "pcie-phy";
286 reset-names = "phy", "mac";
288 #interrupt-cells = <1>;
289 interrupt-map-mask = <0 0 0 0x7>;
290 interrupt-map = <0 0 0 1 &pcie_intc 0>,
291 <0 0 0 2 &pcie_intc 1>,
294 pcie_intc: interrupt-controller {
295 #address-cells = <0>;
296 #interrupt-cells = <1>;
297 interrupt-controller;