Lines Matching +full:0 +full:x1e144000

41            | Device 0 |           | Device 0 |          | Device 0 |
42            |  Func 0  |           |  Func 0  |          |  Func 0  |
55       - description: pcie port 0 RC control registers
63   '^pcie@[0-2],0$':
81         pattern: '^pcie-phy[0-2]$'
113         reg = <0x1e140000 0x100>,
114               <0x1e142000 0x100>,
115               <0x1e143000 0x100>,
116               <0x1e144000 0x100>;
121         pinctrl-0 = <&pcie_pins>;
123         ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>,  /* pci memory */
124                  <0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>;  /* io space */
126         interrupt-map-mask = <0xF800 0 0 0>;
127         interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
128                         <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
129                         <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
132         pcie@0,0 {
133             reg = <0x0000 0 0 0 0>;
138             interrupt-map-mask = <0 0 0 0>;
139             interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
147         pcie@1,0 {
148             reg = <0x0800 0 0 0 0>;
153             interrupt-map-mask = <0 0 0 0>;
154             interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
162         pcie@2,0 {
163             reg = <0x1000 0 0 0 0>;
168             interrupt-map-mask = <0 0 0 0>;
169             interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
172             phys = <&pcie2_phy 0>;