Lines Matching +full:interrupt +full:- +full:map +full:- +full:mask
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/marvell,kirkwood-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
11 - Pali Rohár <pali@kernel.org>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - marvell,armada-370-pcie
20 - marvell,armada-xp-pcie
21 - marvell,dove-pcie
22 - marvell,kirkwood-pcie
32 * r is a 32-bits value that gives the offset of the MMIO registers of
35 * s is a 32-bits value that give the size of this MMIO registers area.
60 msi-parent:
67 - $ref: /schemas/pci/pci-bus-common.yaml#
68 - $ref: /schemas/pci/pci-device.yaml#
79 interrupt-names:
82 - const: intx
83 - const: error
85 reset-delay-us:
89 marvell,pcie-port:
94 marvell,pcie-lane:
99 interrupt-controller:
104 interrupt-controller: true
106 '#interrupt-cells':
110 - assigned-addresses
111 - clocks
112 - interrupt-map
113 - marvell,pcie-port
118 - |
122 #address-cells = <2>;
123 #size-cells = <2>;
126 compatible = "marvell,armada-xp-pcie";
129 #address-cells = <3>;
130 #size-cells = <2>;
132 bus-range = <0x00 0xff>;
133 msi-parent = <&mpic>;
172 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
174 #address-cells = <3>;
175 #size-cells = <2>;
176 #interrupt-cells = <1>;
179 interrupt-map-mask = <0 0 0 0>;
180 interrupt-map = <0 0 0 0 &mpic 58>;
181 marvell,pcie-port = <0>;
182 marvell,pcie-lane = <0>;
183 num-lanes = <1>;
184 /* low-active PERST# reset on GPIO 25 */
185 reset-gpios = <&gpio0 25 1>;
187 reset-delay-us = <20000>;
193 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
195 #address-cells = <3>;
196 #size-cells = <2>;
197 #interrupt-cells = <1>;
200 interrupt-map-mask = <0 0 0 0>;
201 interrupt-map = <0 0 0 0 &mpic 59>;
202 marvell,pcie-port = <0>;
203 marvell,pcie-lane = <1>;
204 num-lanes = <1>;
210 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
212 #address-cells = <3>;
213 #size-cells = <2>;
214 #interrupt-cells = <1>;
217 interrupt-map-mask = <0 0 0 0>;
218 interrupt-map = <0 0 0 0 &mpic 60>;
219 marvell,pcie-port = <0>;
220 marvell,pcie-lane = <2>;
221 num-lanes = <1>;
227 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
229 #address-cells = <3>;
230 #size-cells = <2>;
231 #interrupt-cells = <1>;
234 interrupt-map-mask = <0 0 0 0>;
235 interrupt-map = <0 0 0 0 &mpic 61>;
236 marvell,pcie-port = <0>;
237 marvell,pcie-lane = <3>;
238 num-lanes = <1>;
244 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
246 #address-cells = <3>;
247 #size-cells = <2>;
248 #interrupt-cells = <1>;
251 interrupt-map-mask = <0 0 0 0>;
252 interrupt-map = <0 0 0 0 &mpic 62>;
253 marvell,pcie-port = <1>;
254 marvell,pcie-lane = <0>;
255 num-lanes = <1>;
261 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
263 #address-cells = <3>;
264 #size-cells = <2>;
265 #interrupt-cells = <1>;
268 interrupt-map-mask = <0 0 0 0>;
269 interrupt-map = <0 0 0 0 &mpic 63>;
270 marvell,pcie-port = <1>;
271 marvell,pcie-lane = <1>;
272 num-lanes = <1>;