Lines Matching +full:num +full:- +full:lanes

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Rahul Tanwar <rtanwar@maxlinear.com>
16         const: intel,lgm-pcie
18     - compatible
21   - $ref: /schemas/pci/snps,dw-pcie.yaml#
26       - const: intel,lgm-pcie
27       - const: snps,dw-pcie
31       - description: Controller control and status registers.
32       - description: PCIe configuration registers.
33       - description: Controller application registers.
35   reg-names:
37       - const: dbi
38       - const: config
39       - const: app
53   phy-names:
56   reset-gpios:
59   num-lanes:
62   max-link-speed:
66   reset-assert-ms:
73   - compatible
74   - reg
75   - reg-names
76   - ranges
77   - resets
78   - clocks
79   - phys
80   - phy-names
81   - reset-gpios
82   - '#interrupt-cells'
83   - interrupt-map
84   - interrupt-map-mask
89   - |
90     #include <dt-bindings/gpio/gpio.h>
92       compatible = "intel,lgm-pcie", "snps,dw-pcie";
94       #address-cells = <3>;
95       #size-cells = <2>;
99       reg-names = "dbi", "config", "app";
100       linux,pci-domain = <0>;
101       max-link-speed = <4>;
102       bus-range = <0x00 0x08>;
103       #interrupt-cells = <1>;
104       interrupt-map-mask = <0 0 0 0x7>;
105       interrupt-map = <0 0 0 1 &ioapic1 27 1>,
113       phy-names = "pcie";
114       reset-assert-ms = <500>;
115       reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
116       num-lanes = <2>;