Lines Matching +full:axi +full:- +full:pcie +full:- +full:host +full:- +full:1
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic PCI host controller
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
41 - description:
42 PCIe host controller in Arm Juno based on PLDA XpressRICH3-AXI IP
44 - const: arm,juno-r1-pcie
45 - const: plda,xpressrich3-axi
46 - const: pci-host-ecam-generic
47 - description: |
48 ThunderX PCI host controller for pass-1.x silicon
50 Firmware-initialized PCI host controller to on-chip devices found on
51 some Cavium ThunderX processors. These devices have ECAM-based config
55 const: cavium,pci-host-thunder-ecam
56 - description:
57 Cavium ThunderX PEM firmware-initialized PCIe host controller
58 const: cavium,pci-host-thunder-pem
59 - description:
60 HiSilicon Hip06/Hip07 PCIe host bridge in almost-ECAM mode. Some
61 firmware places the host controller in a mode where it is ECAM
64 - hisilicon,hip06-pcie-ecam
65 - hisilicon,hip07-pcie-ecam
66 - description: |
68 DesignWare PCIe controller in RC mode with static ATU window mappings
78 device #1 and beyond on the first bus.
80 - enum:
81 - marvell,armada8k-pcie-ecam
82 - socionext,synquacer-pcie-ecam
83 - const: snps,dw-pcie-ecam
84 - description:
85 CAM or ECAM compliant PCI host controllers without any quirks
87 - pci-host-cam-generic
88 - pci-host-ecam-generic
93 bus. The base address corresponds to the first bus in the "bus-range"
94 property. If no "bus-range" is specified, this will be bus 0 (the
95 default). Some host controllers have a 2nd non-compliant address range,
97 minItems: 1
102 As described in IEEE Std 1275-1994, but must provide at least a
103 definition of non-prefetchable memory. One or both of prefetchable Memory
106 dma-coherent: true
107 iommu-map: true
108 iommu-map-mask: true
109 msi-parent: true
111 ats-supported:
113 Indicates that a PCIe host controller supports ATS, and can handle Memory
118 - compatible
119 - reg
120 - ranges
123 - $ref: /schemas/pci/pci-host-bridge.yaml#
124 - if:
128 const: arm,juno-r1-pcie
131 - dma-coherent
133 - if:
139 - cavium,pci-host-thunder-pem
140 - hisilicon,hip06-pcie-ecam
141 - hisilicon,hip07-pcie-ecam
145 maxItems: 1
150 - |
153 #address-cells = <2>;
154 #size-cells = <2>;
155 pcie@40000000 {
156 compatible = "pci-host-cam-generic";
158 #address-cells = <3>;
159 #size-cells = <2>;
160 bus-range = <0x0 0x1>;
169 #interrupt-cells = <0x1>;
171 // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(3)
172 interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1>,
177 // PCI_DEVICE(3) INT#(1)
178 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;