Lines Matching +full:msi +full:- +full:map +full:- +full:mask
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
25 - fsl,imx6q-pcie
26 - fsl,imx6sx-pcie
27 - fsl,imx6qp-pcie
28 - fsl,imx7d-pcie
29 - fsl,imx8mq-pcie
30 - fsl,imx8mm-pcie
31 - fsl,imx8mp-pcie
32 - fsl,imx95-pcie
33 - fsl,imx8q-pcie
38 - description: PCIe bridge clock.
39 - description: PCIe bus clock.
40 - description: PCIe PHY clock.
41 - description: Additional required clock entry for imx6sx-pcie,
42 imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
43 - description: PCIe reference clock.
45 clock-names:
51 - description: builtin MSI controller.
53 interrupt-names:
55 - const: msi
57 reset-gpio:
59 reset signal. It's not polarity aware and defaults to active-low reset
62 reset-gpio-active-high:
64 specified in the "reset-gpio" property is reversed (H=reset state,
69 - compatible
70 - reg
71 - reg-names
72 - "#address-cells"
73 - "#size-cells"
74 - device_type
75 - bus-range
76 - ranges
77 - interrupts
78 - interrupt-names
79 - "#interrupt-cells"
80 - interrupt-map-mask
81 - interrupt-map
84 - $ref: /schemas/pci/snps,dw-pcie.yaml#
85 - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
86 - if:
90 - fsl,imx6q-pcie
91 - fsl,imx6sx-pcie
92 - fsl,imx6qp-pcie
93 - fsl,imx7d-pcie
94 - fsl,imx8mq-pcie
95 - fsl,imx8mm-pcie
96 - fsl,imx8mp-pcie
101 reg-names:
103 - const: dbi
104 - const: config
106 - if:
110 - fsl,imx95-pcie
116 reg-names:
118 - const: dbi
119 - const: config
120 - const: atu
121 - const: app
123 - if:
127 - fsl,imx6sx-pcie
132 clock-names:
134 - const: pcie
135 - const: pcie_bus
136 - const: pcie_phy
137 - const: pcie_inbound_axi
139 - if:
143 - fsl,imx8mq-pcie
148 clock-names:
150 - const: pcie
151 - const: pcie_bus
152 - const: pcie_phy
153 - const: pcie_aux
155 - if:
159 - fsl,imx6q-pcie
160 - fsl,imx6qp-pcie
161 - fsl,imx7d-pcie
166 clock-names:
168 - const: pcie
169 - const: pcie_bus
170 - const: pcie_phy
172 - if:
176 - fsl,imx8mm-pcie
177 - fsl,imx8mp-pcie
182 clock-names:
184 - const: pcie
185 - const: pcie_bus
186 - const: pcie_aux
188 - if:
192 - fsl,imx8q-pcie
197 clock-names:
199 - const: dbi
200 - const: mstr
201 - const: slv
203 - if:
207 - fsl,imx95-pcie
212 clock-names:
214 - const: pcie
215 - const: pcie_bus
216 - const: pcie_phy
217 - const: pcie_aux
218 - const: ref
223 - |
224 #include <dt-bindings/clock/imx6qdl-clock.h>
225 #include <dt-bindings/interrupt-controller/arm-gic.h>
228 compatible = "fsl,imx6q-pcie";
231 reg-names = "dbi", "config";
232 #address-cells = <3>;
233 #size-cells = <2>;
235 bus-range = <0x00 0xff>;
238 num-lanes = <1>;
240 interrupt-names = "msi";
241 #interrupt-cells = <1>;
242 interrupt-map-mask = <0 0 0 0x7>;
243 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
250 clock-names = "pcie", "pcie_bus", "pcie_phy";