Lines Matching +full:imx6sx +full:- +full:pcie +full:- +full:ep
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe host controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
25 - fsl,imx6q-pcie
26 - fsl,imx6sx-pcie
27 - fsl,imx6qp-pcie
28 - fsl,imx7d-pcie
29 - fsl,imx8mq-pcie
30 - fsl,imx8mm-pcie
31 - fsl,imx8mp-pcie
32 - fsl,imx95-pcie
33 - fsl,imx8q-pcie
38 - description: PCIe bridge clock.
39 - description: PCIe bus clock.
40 - description: PCIe PHY clock.
41 - description: Additional required clock entry for imx6sx-pcie,
42 imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
44 clock-names:
50 - description: builtin MSI controller.
52 interrupt-names:
54 - const: msi
56 reset-gpio:
58 reset signal. It's not polarity aware and defaults to active-low reset
61 reset-gpio-active-high:
63 specified in the "reset-gpio" property is reversed (H=reset state,
68 - compatible
69 - reg
70 - reg-names
71 - "#address-cells"
72 - "#size-cells"
73 - device_type
74 - bus-range
75 - ranges
76 - interrupts
77 - interrupt-names
78 - "#interrupt-cells"
79 - interrupt-map-mask
80 - interrupt-map
83 - $ref: /schemas/pci/snps,dw-pcie.yaml#
84 - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
85 - if:
89 - fsl,imx6q-pcie
90 - fsl,imx6sx-pcie
91 - fsl,imx6qp-pcie
92 - fsl,imx7d-pcie
93 - fsl,imx8mq-pcie
94 - fsl,imx8mm-pcie
95 - fsl,imx8mp-pcie
100 reg-names:
102 - const: dbi
103 - const: config
105 - if:
109 - fsl,imx95-pcie
115 reg-names:
117 - const: dbi
118 - const: config
119 - const: atu
120 - const: app
122 - if:
126 - fsl,imx6sx-pcie
131 clock-names:
133 - const: pcie
134 - const: pcie_bus
135 - const: pcie_phy
136 - const: pcie_inbound_axi
138 - if:
142 - fsl,imx8mq-pcie
143 - fsl,imx95-pcie
148 clock-names:
150 - const: pcie
151 - const: pcie_bus
152 - const: pcie_phy
153 - const: pcie_aux
155 - if:
159 - fsl,imx6q-pcie
160 - fsl,imx6qp-pcie
161 - fsl,imx7d-pcie
166 clock-names:
168 - const: pcie
169 - const: pcie_bus
170 - const: pcie_phy
172 - if:
176 - fsl,imx8mm-pcie
177 - fsl,imx8mp-pcie
182 clock-names:
184 - const: pcie
185 - const: pcie_bus
186 - const: pcie_aux
188 - if:
192 - fsl,imx8q-pcie
197 clock-names:
199 - const: dbi
200 - const: mstr
201 - const: slv
206 - |
207 #include <dt-bindings/clock/imx6qdl-clock.h>
208 #include <dt-bindings/interrupt-controller/arm-gic.h>
210 pcie: pcie@1ffc000 {
211 compatible = "fsl,imx6q-pcie";
214 reg-names = "dbi", "config";
215 #address-cells = <3>;
216 #size-cells = <2>;
218 bus-range = <0x00 0xff>;
221 num-lanes = <1>;
223 interrupt-names = "msi";
224 #interrupt-cells = <1>;
225 interrupt-map-mask = <0 0 0 0x7>;
226 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
233 clock-names = "pcie", "pcie_bus", "pcie_phy";