Lines Matching +full:imx6sx +full:- +full:pcie +full:- +full:ep
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe Endpoint controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 This PCIe controller is based on the Synopsys DesignWare PCIe IP and
15 thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
22 - fsl,imx8mm-pcie-ep
23 - fsl,imx8mq-pcie-ep
24 - fsl,imx8mp-pcie-ep
25 - fsl,imx95-pcie-ep
30 - description: PCIe bridge clock.
31 - description: PCIe bus clock.
32 - description: PCIe PHY clock.
33 - description: Additional required clock entry for imx6sx-pcie,
34 imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
36 clock-names:
42 - description: builtin eDMA interrupter.
44 interrupt-names:
46 - const: dma
49 - compatible
50 - reg
51 - reg-names
52 - interrupts
53 - interrupt-names
56 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
57 - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
58 - if:
62 - fsl,imx8mm-pcie-ep
63 - fsl,imx8mq-pcie-ep
64 - fsl,imx8mp-pcie-ep
70 reg-names:
72 - const: dbi
73 - const: addr_space
74 - const: dbi2
75 - const: atu
77 - if:
81 - fsl,imx95-pcie-ep
87 reg-names:
89 - const: dbi
90 - const: atu
91 - const: dbi2
92 - const: app
93 - const: dma
94 - const: addr_space
96 - if:
100 - fsl,imx8mq-pcie-ep
101 - fsl,imx95-pcie-ep
106 clock-names:
108 - const: pcie
109 - const: pcie_bus
110 - const: pcie_phy
111 - const: pcie_aux
116 clock-names:
118 - const: pcie
119 - const: pcie_bus
120 - const: pcie_aux
126 - |
127 #include <dt-bindings/clock/imx8mp-clock.h>
128 #include <dt-bindings/power/imx8mp-power.h>
129 #include <dt-bindings/reset/imx8mp-reset.h>
130 #include <dt-bindings/interrupt-controller/arm-gic.h>
132 pcie_ep: pcie-ep@33800000 {
133 compatible = "fsl,imx8mp-pcie-ep";
138 reg-names = "dbi", "addr_space", "dbi2", "atu";
142 clock-names = "pcie", "pcie_bus", "pcie_aux";
143 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
144 assigned-clock-rates = <10000000>;
145 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
146 num-lanes = <1>;
148 interrupt-names = "dma";
149 fsl,max-link-speed = <3>;
150 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
153 reset-names = "apps", "turnoff";
155 phy-names = "pcie-phy";
156 num-ib-windows = <4>;
157 num-ob-windows = <4>;