Lines Matching +full:imx7d +full:- +full:pcie +full:- +full:ep
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe RC/EP controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 Generic Freescale i.MX PCIe Root Port and Endpoint controller
22 clock-names:
26 num-lanes:
29 fsl,imx7d-pcie-phy:
31 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
32 required properties for imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie,
33 and imx8mq-pcie-ep.
35 power-domains:
38 - description: The phandle pointing to the DISPLAY domain for
39 imx6sx-pcie, imx6sx-pcie-ep, to PCIE_PHY power domain for
40 imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie and imx8mq-pcie-ep.
41 - description: The phandle pointing to the PCIE_PHY power domains
42 for imx6sx-pcie and imx6sx-pcie-ep.
44 power-domain-names:
47 - const: pcie
48 - const: pcie_phy
53 description: Phandles to PCIe-related reset lines exposed by SRC
54 IP block. Additional required by imx7d-pcie, imx7d-pcie-ep,
55 imx8mq-pcie, and imx8mq-pcie-ep.
57 reset-names:
61 fsl,tx-deemph-gen1:
62 description: Gen1 De-emphasis value (optional required).
66 fsl,tx-deemph-gen2-3p5db:
67 description: Gen2 (3.5db) De-emphasis value (optional required).
71 fsl,tx-deemph-gen2-6db:
72 description: Gen2 (6db) De-emphasis value (optional required).
76 fsl,tx-swing-full:
81 fsl,tx-swing-low:
86 fsl,max-link-speed:
98 phy-names:
99 const: pcie-phy
101 vpcie-supply:
102 description: Should specify the regulator in charge of PCIe port power.
103 The regulator will be enabled when initializing the PCIe host and
107 vph-supply:
109 the three PCIe PHY powers. This regulator can be supplied by both
113 - clocks
114 - clock-names
115 - num-lanes
118 - if:
123 - fsl,imx6sx-pcie
124 - fsl,imx6sx-pcie-ep
127 clock-names:
129 - {}
130 - {}
131 - const: pcie_phy
132 - const: pcie_inbound_axi
133 power-domains:
135 power-domain-names:
138 - if:
143 - fsl,imx8mq-pcie
144 - fsl,imx8mq-pcie-ep
147 clock-names:
149 - {}
150 - {}
151 - const: pcie_phy
152 - const: pcie_aux
154 - if:
159 - fsl,imx6q-pcie
160 - fsl,imx6qp-pcie
161 - fsl,imx7d-pcie
162 - fsl,imx6q-pcie-ep
163 - fsl,imx6qp-pcie-ep
164 - fsl,imx7d-pcie-ep
167 clock-names:
172 - if:
177 - fsl,imx8mm-pcie
178 - fsl,imx8mp-pcie
179 - fsl,imx8mm-pcie-ep
180 - fsl,imx8mp-pcie-ep
183 clock-names:
187 - if:
192 - fsl,imx6q-pcie
193 - fsl,imx6qp-pcie
194 - fsl,imx6q-pcie-ep
195 - fsl,imx6qp-pcie-ep
198 power-domains: false
199 power-domain-names: false
201 - if:
207 - fsl,imx6sx-pcie
208 - fsl,imx6q-pcie
209 - fsl,imx6qp-pcie
210 - fsl,imx95-pcie
211 - fsl,imx6sx-pcie-ep
212 - fsl,imx6q-pcie-ep
213 - fsl,imx6qp-pcie-ep
216 power-domains:
218 power-domain-names: false
220 - if:
225 - fsl,imx6q-pcie
226 - fsl,imx6sx-pcie
227 - fsl,imx6qp-pcie
228 - fsl,imx7d-pcie
229 - fsl,imx8mq-pcie
230 - fsl,imx6q-pcie-ep
231 - fsl,imx6sx-pcie-ep
232 - fsl,imx6qp-pcie-ep
233 - fsl,imx7d-pcie-ep
234 - fsl,imx8mq-pcie-ep
239 reset-names:
241 - const: pciephy
242 - const: apps
243 - const: turnoff
248 reset-names:
250 - const: apps
251 - const: turnoff