Lines Matching +full:bt1 +full:- +full:ccu
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
18 performed by software. There four in- and four outbound iATU regions
22 - $ref: /schemas/pci/snps,dw-pcie.yaml#
26 const: baikal,bt1-pcie
30 DBI, DBI2 and at least 4KB outbound iATU-capable region for the
31 peripheral devices CFG-space access.
34 reg-names:
36 - const: dbi
37 - const: dbi2
38 - const: config
42 MSI, AER, PME, Hot-plug, Link Bandwidth Management, Link Equalization
46 interrupt-names:
48 - const: dma0
49 - const: dma1
50 - const: dma2
51 - const: dma3
52 - const: dma4
53 - const: dma5
54 - const: dma6
55 - const: dma7
56 - const: msi
57 - const: aer
58 - const: pme
59 - const: hp
60 - const: bw_mg
61 - const: l_eq
65 DBI (attached to the APB bus), AXI-bus master and slave interfaces
67 clock signal is supposed to be attached to the corresponding Ref-pad
69 sub-modules (pipe, core, aux, etc).
72 clock-names:
74 - const: dbi
75 - const: mstr
76 - const: slv
77 - const: ref
83 signals are exposed via the system CCU module.
86 reset-names:
88 - const: mstr
89 - const: slv
90 - const: pwr
91 - const: hot
92 - const: phy
93 - const: core
94 - const: pipe
95 - const: sticky
96 - const: non-sticky
98 baikal,bt1-syscon:
101 Phandle to the Baikal-T1 System Controller DT node. It's required to
102 access some additional PM, Reset-related and LTSSM signals.
104 num-lanes:
107 max-link-speed:
111 - compatible
112 - reg
113 - reg-names
114 - interrupts
115 - interrupt-names
120 - |
121 #include <dt-bindings/interrupt-controller/mips-gic.h>
122 #include <dt-bindings/gpio/gpio.h>
125 compatible = "baikal,bt1-pcie";
128 reg-names = "dbi", "dbi2", "config";
129 #address-cells = <3>;
130 #size-cells = <2>;
133 bus-range = <0x0 0xff>;
149 interrupt-names = "dma0", "dma1", "dma2", "dma3",
155 clock-names = "dbi", "mstr", "slv", "ref";
160 reset-names = "mstr", "slv", "pwr", "hot", "phy", "core", "pipe",
161 "sticky", "non-sticky";
163 reset-gpios = <&port0 0 GPIO_ACTIVE_LOW>;
165 num-lanes = <4>;
166 max-link-speed = <3>;