Lines Matching +full:supported +full:- +full:hw
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
23 the OPP framework with required information (existing HW bitmap).
25 operating-points-v2 table when it is parsed by the OPP framework.
30 - operating-points-v2-krait-cpu
31 - operating-points-v2-kryo-cpu
33 nvmem-cells:
35 A phandle pointing to a nvmem-cells node representing the
40 opp-shared: true
43 '^opp-?[0-9]+$':
48 opp-hz: true
50 opp-microvolt: true
52 opp-peak-kBps: true
54 opp-supported-hw:
56 A single 32 bit bitmap value, representing compatible HW.
62 4-31: unused
65 0-3: unused
69 7-31: unused
75 3-31: unused
79 clock-latency-ns: true
81 required-opps: true
84 '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true
87 - opp-hz
90 - compatible
94 - nvmem-cells
97 '^opp-?[0-9]+$':
99 - opp-supported-hw
104 - |
107 compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
108 #address-cells = <2>;
109 #size-cells = <2>;
112 #address-cells = <2>;
113 #size-cells = <0>;
119 enable-method = "psci";
120 cpu-idle-states = <&CPU_SLEEP_0>;
121 capacity-dmips-mhz = <1024>;
123 operating-points-v2 = <&cluster0_opp>;
124 power-domains = <&cpr>;
125 power-domain-names = "cpr";
126 #cooling-cells = <2>;
127 next-level-cache = <&L2_0>;
128 L2_0: l2-cache {
130 cache-level = <2>;
131 cache-unified;
139 enable-method = "psci";
140 cpu-idle-states = <&CPU_SLEEP_0>;
141 capacity-dmips-mhz = <1024>;
143 operating-points-v2 = <&cluster0_opp>;
144 power-domains = <&cpr>;
145 power-domain-names = "cpr";
146 #cooling-cells = <2>;
147 next-level-cache = <&L2_0>;
154 enable-method = "psci";
155 cpu-idle-states = <&CPU_SLEEP_0>;
156 capacity-dmips-mhz = <1024>;
158 operating-points-v2 = <&cluster1_opp>;
159 power-domains = <&cpr>;
160 power-domain-names = "cpr";
161 #cooling-cells = <2>;
162 next-level-cache = <&L2_1>;
163 L2_1: l2-cache {
165 cache-level = <2>;
166 cache-unified;
174 enable-method = "psci";
175 cpu-idle-states = <&CPU_SLEEP_0>;
176 capacity-dmips-mhz = <1024>;
178 operating-points-v2 = <&cluster1_opp>;
179 power-domains = <&cpr>;
180 power-domain-names = "cpr";
181 #cooling-cells = <2>;
182 next-level-cache = <&L2_1>;
185 cpu-map {
208 cluster0_opp: opp-table-0 {
209 compatible = "operating-points-v2-kryo-cpu";
210 nvmem-cells = <&speedbin_efuse>;
211 opp-shared;
213 opp-307200000 {
214 opp-hz = /bits/ 64 <307200000>;
215 opp-microvolt = <905000 905000 1140000>;
216 opp-supported-hw = <0x7>;
217 clock-latency-ns = <200000>;
218 required-opps = <&cpr_opp1>;
220 opp-1401600000 {
221 opp-hz = /bits/ 64 <1401600000>;
222 opp-microvolt = <1140000 905000 1140000>;
223 opp-supported-hw = <0x5>;
224 clock-latency-ns = <200000>;
225 required-opps = <&cpr_opp2>;
227 opp-1593600000 {
228 opp-hz = /bits/ 64 <1593600000>;
229 opp-microvolt = <1140000 905000 1140000>;
230 opp-supported-hw = <0x1>;
231 clock-latency-ns = <200000>;
232 required-opps = <&cpr_opp3>;
236 cluster1_opp: opp-table-1 {
237 compatible = "operating-points-v2-kryo-cpu";
238 nvmem-cells = <&speedbin_efuse>;
239 opp-shared;
241 opp-307200000 {
242 opp-hz = /bits/ 64 <307200000>;
243 opp-microvolt = <905000 905000 1140000>;
244 opp-supported-hw = <0x7>;
245 clock-latency-ns = <200000>;
246 required-opps = <&cpr_opp1>;
248 opp-1804800000 {
249 opp-hz = /bits/ 64 <1804800000>;
250 opp-microvolt = <1140000 905000 1140000>;
251 opp-supported-hw = <0x6>;
252 clock-latency-ns = <200000>;
253 required-opps = <&cpr_opp4>;
255 opp-1900800000 {
256 opp-hz = /bits/ 64 <1900800000>;
257 opp-microvolt = <1140000 905000 1140000>;
258 opp-supported-hw = <0x4>;
259 clock-latency-ns = <200000>;
260 required-opps = <&cpr_opp5>;
262 opp-2150400000 {
263 opp-hz = /bits/ 64 <2150400000>;
264 opp-microvolt = <1140000 905000 1140000>;
265 opp-supported-hw = <0x1>;
266 clock-latency-ns = <200000>;
267 required-opps = <&cpr_opp6>;
271 /* Dummy opp table to give example for named opp-microvolt */
272 opp-table-2 {
273 compatible = "operating-points-v2-krait-cpu";
274 nvmem-cells = <&speedbin_efuse>;
276 opp-384000000 {
277 opp-hz = /bits/ 64 <384000000>;
278 opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>;
279 opp-microvolt-speed0-pvs1 = <925000 878750 971250>;
280 opp-microvolt-speed0-pvs2 = <875000 831250 918750>;
281 opp-microvolt-speed0-pvs3 = <800000 760000 840000>;
282 opp-supported-hw = <0x7>;
283 clock-latency-ns = <100000>;
289 memory-region = <&smem_mem>;
294 #address-cells = <1>;
295 #size-cells = <1>;
298 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
300 #address-cells = <1>;
301 #size-cells = <1>;