Lines Matching +full:output +full:- +full:impedance
1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
44 ti,min-output-impedance:
47 MAC Interface Impedance control to set the programmable output impedance
50 ti,max-output-impedance:
53 MAC Interface Impedance control to set the programmable output impedance
56 ti,min-output-impedance, ti,max-output-impedance properties
58 cell takes precedence over ti,max-output-impedance, which in
59 turn takes precedence over ti,min-output-impedance.
61 tx-fifo-depth:
64 Transmitt FIFO depth see dt-bindings/net/ti-dp83867.h for values
66 rx-fifo-depth:
69 Receive FIFO depth see dt-bindings/net/ti-dp83867.h for values
71 ti,clk-output-sel:
74 Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h
78 ti,rx-internal-delay:
81 RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
85 ti,tx-internal-delay:
88 RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
97 should use "rgmii-id" if internal delays are desired as this may be
100 ti,dp83867-rxctrl-strap-quirk:
108 ti,sgmii-ref-clock-output-enable:
111 This denotes which SGMII configuration is used (4 or 6-wire modes).
114 ti,fifo-depth:
118 Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable
122 - reg
127 - |
128 #include <dt-bindings/net/ti-dp83867.h>
130 #address-cells = <1>;
131 #size-cells = <0>;
132 ethphy0: ethernet-phy@0 {
134 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
135 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
136 ti,max-output-impedance;
137 ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_RCLK>;
138 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
139 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;