Lines Matching +full:loss +full:- +full:of +full:- +full:signal

1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11   - Andrew Davis <afd@ti.com>
14   The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
15   provides all of the physical layer functions needed to transmit and receive
16   data over standard, twisted-pair cables or to connect to an external,
17   fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24   - $ref: ethernet-phy.yaml#
30   ti,link-loss-low:
34        Sets the DP83822 to detect a link drop condition when the signal goes
35        high.  If not set then link drop will occur when the signal goes low.
39   ti,fiber-mode:
46        If the fiber mode is not strapped then signal detection for the PHY
48        In fiber mode, auto-negotiation is disabled and the PHY can only work in
49        100base-fx (full and half duplex) modes.
51   rx-internal-delay-ps:
54        Setting this property to a non-zero number sets the RX internal delay
58   tx-internal-delay-ps:
61        Setting this property to a non-zero number sets the TX internal delay
65   ti,cfg-dac-minus-one-bp:
69        of the logical level -1 for the MLT-3 encoded TX data.
74   ti,cfg-dac-plus-one-bp:
78        of the logical level +1 for the MLT-3 encoded TX data.
83   ti,rmii-mode:
87          - RMII master, where the PHY outputs a 50MHz reference clock which can
89          - RMII slave, where the PHY expects a 50MHz reference clock input
96       - master
97       - slave
100   - reg
105   - |
107       #address-cells = <1>;
108       #size-cells = <0>;
109       ethphy0: ethernet-phy@0 {
111         rx-internal-delay-ps = <1>;
112         tx-internal-delay-ps = <1>;