Lines Matching +full:ether +full:- +full:r8a7790
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
20 - renesas,etheravb-r8a7745 # RZ/G1E
21 - renesas,etheravb-r8a77470 # RZ/G1C
22 - renesas,etheravb-r8a7790 # R-Car H2
23 - renesas,etheravb-r8a7791 # R-Car M2-W
24 - renesas,etheravb-r8a7792 # R-Car V2H
25 - renesas,etheravb-r8a7793 # R-Car M2-N
26 - renesas,etheravb-r8a7794 # R-Car E2
27 - const: renesas,etheravb-rcar-gen2 # R-Car Gen2 and RZ/G1
29 - items:
30 - enum:
31 - renesas,etheravb-r8a774a1 # RZ/G2M
32 - renesas,etheravb-r8a774b1 # RZ/G2N
33 - renesas,etheravb-r8a774c0 # RZ/G2E
34 - renesas,etheravb-r8a774e1 # RZ/G2H
35 - renesas,etheravb-r8a7795 # R-Car H3
36 - renesas,etheravb-r8a7796 # R-Car M3-W
37 - renesas,etheravb-r8a77961 # R-Car M3-W+
38 - renesas,etheravb-r8a77965 # R-Car M3-N
39 - renesas,etheravb-r8a77970 # R-Car V3M
40 - renesas,etheravb-r8a77980 # R-Car V3H
41 - renesas,etheravb-r8a77990 # R-Car E3
42 - renesas,etheravb-r8a77995 # R-Car D3
43 - const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2
45 - items:
46 - enum:
47 - renesas,etheravb-r8a779a0 # R-Car V3U
48 - renesas,etheravb-r8a779g0 # R-Car V4H
49 - renesas,etheravb-r8a779h0 # R-Car V4M
50 - const: renesas,etheravb-rcar-gen4 # R-Car Gen4
52 - items:
53 - enum:
54 - renesas,etheravb-r9a09g011 # RZ/V2M
55 - const: renesas,etheravb-rzv2m # RZ/V2M compatible
57 - items:
58 - enum:
59 - renesas,r9a07g043-gbeth # RZ/G2UL and RZ/Five
60 - renesas,r9a07g044-gbeth # RZ/G2{L,LC}
61 - renesas,r9a07g054-gbeth # RZ/V2L
62 - renesas,r9a08g045-gbeth # RZ/G3S
63 - const: renesas,rzg2l-gbeth # RZ/{G2L,G2UL,V2L} family
68 - description: MAC register block
69 - description: Stream buffer
75 interrupt-names:
83 clock-names:
90 power-domains:
96 phy-mode: true
98 phy-handle: true
100 '#address-cells':
105 '#size-cells':
114 renesas,no-ether-link:
119 renesas,ether-link-active-low:
122 Specify when the AVB_LINK signal is active-low instead of normal
123 active-high.
125 rx-internal-delay-ps:
128 tx-internal-delay-ps:
131 # In older bindings there where no mdio child-node to describe the MDIO bus
133 # users should describe the PHY inside the mdio child-node.
135 "@[0-9a-f]$":
140 - compatible
141 - reg
142 - interrupts
143 - clocks
144 - power-domains
145 - resets
146 - phy-mode
147 - phy-handle
150 - $ref: ethernet-controller.yaml#
152 - if:
157 - renesas,etheravb-rcar-gen2
158 - renesas,etheravb-r8a7795
159 - renesas,etheravb-r8a7796
160 - renesas,etheravb-r8a77961
161 - renesas,etheravb-r8a77965
171 - if:
176 - renesas,etheravb-rcar-gen2
177 - renesas,rzg2l-gbeth
183 interrupt-names:
186 - const: mux
187 - const: fil
188 - const: arp_ns
189 rx-internal-delay-ps: false
195 const: renesas,etheravb-rzv2m
201 interrupt-names:
203 pattern: '^(ch(1?)[0-9])|ch20|ch21|dia|dib|err_a|err_b|mgmt_a|mgmt_b|line3$'
204 rx-internal-delay-ps: false
206 - interrupt-names
212 interrupt-names:
214 pattern: '^ch[0-9]+$'
216 - interrupt-names
217 - rx-internal-delay-ps
219 - if:
224 - renesas,etheravb-r8a774a1
225 - renesas,etheravb-r8a774b1
226 - renesas,etheravb-r8a774e1
227 - renesas,etheravb-r8a7795
228 - renesas,etheravb-r8a7796
229 - renesas,etheravb-r8a77961
230 - renesas,etheravb-r8a77965
231 - renesas,etheravb-r8a77970
232 - renesas,etheravb-r8a77980
233 - renesas,etheravb-rcar-gen4
236 - tx-internal-delay-ps
239 tx-internal-delay-ps: false
241 - if:
245 const: renesas,etheravb-r8a77995
248 rx-internal-delay-ps:
251 - if:
255 const: renesas,etheravb-r8a77980
258 tx-internal-delay-ps:
261 - if:
265 const: renesas,rzg2l-gbeth
270 - description: Main clock
271 - description: Register access clock
272 - description: Reference clock for RGMII
273 clock-names:
275 - const: axi
276 - const: chi
277 - const: refclk
283 const: renesas,etheravb-rzv2m
288 - description: Main clock
289 - description: Coherent Hub Interface clock
290 - description: gPTP reference clock
291 clock-names:
293 - const: axi
294 - const: chi
295 - const: gptp
301 - description: AVB functional clock
302 - description: Optional TXC reference clock
303 clock-names:
306 - const: fck
307 - const: refclk
312 - |
313 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
314 #include <dt-bindings/interrupt-controller/arm-gic.h>
315 #include <dt-bindings/power/r8a7795-sysc.h>
316 #include <dt-bindings/gpio/gpio.h>
322 compatible = "renesas,etheravb-r8a7795",
323 "renesas,etheravb-rcar-gen3";
350 interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6",
355 clock-names = "fck";
357 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
359 phy-mode = "rgmii";
360 phy-handle = <&phy0>;
361 rx-internal-delay-ps = <0>;
362 tx-internal-delay-ps = <2000>;
363 #address-cells = <1>;
364 #size-cells = <0>;
366 phy0: ethernet-phy@0 {
367 compatible = "ethernet-phy-id0022.1622",
368 "ethernet-phy-ieee802.3-c22";
369 rxc-skew-ps = <1500>;
371 interrupt-parent = <&gpio2>;
373 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;