Lines Matching +full:rx +full:- +full:internal +full:- +full:delay +full:- +full:ps
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
12 - Daniel Machon <daniel.machon@microchip.com>
15 The SparX-5 Enterprise Ethernet switch family provides a rich set of
16 Enterprise switching features such as advanced TCAM-based VLAN and
18 security through TCAM-based frame processing using versatile content
26 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
29 The SparX-5 switch family targets managed Layer 2 and Layer 3
35 pattern: "^switch@[0-9a-f]+$"
39 - enum:
40 - microchip,lan9691-switch
41 - microchip,sparx5-switch
42 - items:
43 - enum:
44 - microchip,lan969c-switch
45 - microchip,lan969b-switch
46 - microchip,lan969a-switch
47 - microchip,lan9699-switch
48 - microchip,lan9698-switch
49 - microchip,lan9697-switch
50 - microchip,lan9696-switch
51 - microchip,lan9695-switch
52 - microchip,lan9694-switch
53 - microchip,lan9693-switch
54 - microchip,lan9692-switch
55 - const: microchip,lan9691-switch
60 - description: cpu target
61 - description: devices target
62 - description: general control block target
64 reg-names:
67 - const: cpu
68 - const: devices
69 - const: gcb
74 - description: register based extraction
75 - description: frame dma based extraction
76 - description: ptp interrupt
78 interrupt-names:
81 - const: xtr
82 - const: fdma
83 - const: ptp
87 - description: Reset controller used for switch core reset (soft reset)
89 reset-names:
91 - const: switch
93 mac-address: true
95 ethernet-ports:
100 '#address-cells':
102 '#size-cells':
106 "^port@[0-9a-f]+$":
107 $ref: /schemas/net/ethernet-controller.yaml#
125 microchip,sd-sgpio:
134 rx-internal-delay-ps:
136 RGMII Receive Clock Delay defined in pico seconds, used to select
137 the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
138 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
139 any delay. The Default is no delay.
143 tx-internal-delay-ps:
145 RGMII Transmit Clock Delay defined in pico seconds, used to select
146 the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
147 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
148 any delay. The Default is no delay.
153 - reg
154 - phys
155 - phy-mode
156 - microchip,bandwidth
159 - required:
160 - phy-handle
161 - required:
162 - sfp
163 - managed
166 - compatible
167 - reg
168 - reg-names
169 - interrupts
170 - interrupt-names
171 - ethernet-ports
174 - if:
179 - microchip,lan9691-switch
184 reg-names:
190 reg-names:
196 - |
197 #include <dt-bindings/interrupt-controller/arm-gic.h>
199 compatible = "microchip,sparx5-switch";
203 reg-names = "cpu", "devices", "gcb";
205 interrupt-names = "xtr";
207 reset-names = "switch";
208 ethernet-ports {
209 #address-cells = <1>;
210 #size-cells = <0>;
216 phy-handle = <&phy0>;
217 phy-mode = "qsgmii";
225 phy-mode = "10gbase-r";
227 managed = "in-band-status";
228 microchip,sd-sgpio = <365>;
234 phy-mode = "10gbase-r";
236 managed = "in-band-status";
237 microchip,sd-sgpio = <369>;
243 phy-mode = "10gbase-r";
245 managed = "in-band-status";
246 microchip,sd-sgpio = <373>;
252 phy-mode = "10gbase-r";
254 managed = "in-band-status";
255 microchip,sd-sgpio = <377>;
262 phy-handle = <&phy64>;
263 phy-mode = "sgmii";
264 mac-address = [ 00 00 00 01 02 03 ];