Lines Matching +full:ptp +full:- +full:ref
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
20 pattern: "^switch@[0-9a-f]+$"
23 const: microchip,lan966x-switch
27 - description: cpu target
28 - description: general control block target
30 reg-names:
32 - const: cpu
33 - const: gcb
38 - description: register based extraction
39 - description: frame dma based extraction
40 - description: analyzer interrupt
41 - description: ptp interrupt
42 - description: ptp external interrupt
44 interrupt-names:
47 - const: xtr
48 - const: fdma
49 - const: ana
50 - const: ptp
51 - const: ptp-ext
55 - description: Reset controller used for switch core reset (soft reset)
57 reset-names:
59 - const: switch
61 ethernet-ports:
65 '#address-cells':
67 '#size-cells':
73 "^port@[0-9a-f]+$":
76 $ref: /schemas/net/ethernet-controller.yaml#
80 '#address-cells':
82 '#size-cells':
93 phy-mode:
98 - gmii
99 - sgmii
100 - qsgmii
101 - 1000base-x
102 - 2500base-x
104 phy-handle:
115 - reg
116 - phys
117 - phy-mode
120 - required:
121 - phy-handle
122 - required:
123 - sfp
124 - managed
127 - compatible
128 - reg
129 - reg-names
130 - interrupts
131 - interrupt-names
132 - resets
133 - reset-names
134 - ethernet-ports
139 - |
140 #include <dt-bindings/interrupt-controller/arm-gic.h>
142 compatible = "microchip,lan966x-switch";
145 reg-names = "cpu", "gcb";
147 interrupt-names = "xtr";
149 reset-names = "switch";
150 ethernet-ports {
151 #address-cells = <1>;
152 #size-cells = <0>;
156 phy-handle = <&phy0>;
158 phy-mode = "gmii";
164 managed = "in-band-status";
166 phy-mode = "sgmii";