Lines Matching +full:rxc +full:- +full:inverse
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
33 - items:
34 - enum:
35 - mediatek,mt2712-gmac
36 - const: snps,dwmac-4.20a
37 - items:
38 - enum:
39 - mediatek,mt8195-gmac
40 - const: snps,dwmac-5.10a
41 - items:
42 - enum:
43 - mediatek,mt8188-gmac
44 - const: mediatek,mt8195-gmac
45 - const: snps,dwmac-5.10a
50 - description: AXI clock
51 - description: APB clock
52 - description: MAC Main clock
53 - description: PTP clock
54 - description: RMII reference clock provided by MAC
55 - description: MAC clock gate
57 clock-names:
60 - const: axi
61 - const: apb
62 - const: mac_main
63 - const: ptp_ref
64 - const: rmii_internal
65 - const: mac_cg
70 interrupt-names:
73 power-domains:
82 mediatek,tx-delay-ps:
92 mediatek,rx-delay-ps:
102 mediatek,rmii-rxc:
106 PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin.
108 mediatek,rmii-clk-from-mac:
114 mediatek,txc-inverse:
124 mediatek,rxc-inverse:
134 mediatek,mac-wol:
137 If present, indicates that MAC supports WOL(Wake-On-LAN), and MAC WOL will be enabled.
141 - compatible
142 - reg
143 - interrupts
144 - interrupt-names
145 - clocks
146 - clock-names
147 - phy-mode
148 - mediatek,pericfg
153 - |
154 #include <dt-bindings/clock/mt2712-clk.h>
155 #include <dt-bindings/gpio/gpio.h>
156 #include <dt-bindings/interrupt-controller/arm-gic.h>
157 #include <dt-bindings/interrupt-controller/irq.h>
158 #include <dt-bindings/power/mt2712-power.h>
161 compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
164 interrupt-names = "macirq";
165 phy-mode = "rgmii-rxid";
166 mac-address = [00 55 7b b5 7d f7];
167 clock-names = "axi",
177 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
180 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
183 power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
185 mediatek,tx-delay-ps = <1530>;
188 snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
189 snps,reset-delays-us = <0 10000 10000>;