Lines Matching +full:syscon +full:- +full:pcie +full:- +full:mode
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
25 - mediatek,mt7981-eth
26 - mediatek,mt7986-eth
27 - mediatek,mt7988-eth
28 - ralink,rt5350-eth
37 clock-names:
45 interrupt-names:
48 - const: fe0
49 - const: fe1
50 - const: fe2
51 - const: fe3
52 - const: pdma0
53 - const: pdma1
54 - const: pdma2
55 - const: pdma3
57 power-domains:
63 reset-names:
65 - const: fe
66 - const: gmac
67 - const: ppe
76 Phandle to the syscon node that handles the port setup.
78 cci-control-port: true
89 Phandle to the syscon node that handles the path from GMAC to
92 mediatek,pcie-mirror:
95 Phandle to the mediatek pcie-mirror controller.
100 Phandle to the syscon node that handles the ports slew rate and
104 $ref: /schemas/types.yaml#/definitions/phandle-array
110 A list of phandle to the syscon node that handles the SGMII setup which is required for
114 $ref: /schemas/types.yaml#/definitions/phandle-array
122 mediatek,wed-pcie:
125 Phandle to the mediatek wed-pcie controller.
127 dma-coherent: true
129 mdio-bus:
133 "#address-cells":
136 "#size-cells":
140 - $ref: ethernet-controller.yaml#
141 - if:
146 - mediatek,mt2701-eth
147 - mediatek,mt7623-eth
154 interrupt-names:
162 clock-names:
164 - const: ethif
165 - const: esw
166 - const: gp1
167 - const: gp2
175 mediatek,wed-pcie: false
180 - if:
185 - mediatek,mt7621-eth
191 interrupt-names:
198 clock-names:
200 - const: ethif
201 - const: fe
209 mediatek,wed-pcie: false
211 - if:
215 const: mediatek,mt7622-eth
222 interrupt-names:
230 clock-names:
232 - const: ethif
233 - const: esw
234 - const: gp0
235 - const: gp1
236 - const: gp2
237 - const: sgmii_tx250m
238 - const: sgmii_rx250m
239 - const: sgmii_cdr_ref
240 - const: sgmii_cdr_fb
241 - const: sgmii_ck
242 - const: eth2pll
252 mediatek,wed-pcie: false
255 mediatek,pcie-mirror: false
257 - if:
261 const: mediatek,mt7629-eth
268 interrupt-names:
276 clock-names:
278 - const: ethif
279 - const: sgmiitop
280 - const: esw
281 - const: gp0
282 - const: gp1
283 - const: gp2
284 - const: fe
285 - const: sgmii_tx250m
286 - const: sgmii_rx250m
287 - const: sgmii_cdr_ref
288 - const: sgmii_cdr_fb
289 - const: sgmii2_tx250m
290 - const: sgmii2_rx250m
291 - const: sgmii2_cdr_ref
292 - const: sgmii2_cdr_fb
293 - const: sgmii_ck
294 - const: eth2pll
304 mediatek,wed-pcie: false
306 - if:
310 const: mediatek,mt7981-eth
316 interrupt-names:
323 clock-names:
325 - const: fe
326 - const: gp2
327 - const: gp1
328 - const: wocpu0
329 - const: sgmii_ck
330 - const: sgmii_tx250m
331 - const: sgmii_rx250m
332 - const: sgmii_cdr_ref
333 - const: sgmii_cdr_fb
334 - const: sgmii2_tx250m
335 - const: sgmii2_rx250m
336 - const: sgmii2_cdr_ref
337 - const: sgmii2_cdr_fb
338 - const: netsys0
339 - const: netsys1
347 - if:
351 const: mediatek,mt7986-eth
357 interrupt-names:
364 clock-names:
366 - const: fe
367 - const: gp2
368 - const: gp1
369 - const: wocpu1
370 - const: wocpu0
371 - const: sgmii_tx250m
372 - const: sgmii_rx250m
373 - const: sgmii_cdr_ref
374 - const: sgmii_cdr_fb
375 - const: sgmii2_tx250m
376 - const: sgmii2_rx250m
377 - const: sgmii2_cdr_ref
378 - const: sgmii2_cdr_fb
379 - const: netsys0
380 - const: netsys1
388 - if:
392 const: mediatek,mt7988-eth
398 interrupt-names:
405 clock-names:
407 - const: crypto
408 - const: fe
409 - const: gp2
410 - const: gp1
411 - const: gp3
412 - const: ethwarp_wocpu2
413 - const: ethwarp_wocpu1
414 - const: ethwarp_wocpu0
415 - const: esw
416 - const: top_eth_gmii_sel
417 - const: top_eth_refck_50m_sel
418 - const: top_eth_sys_200m_sel
419 - const: top_eth_sys_sel
420 - const: top_eth_xgmii_sel
421 - const: top_eth_mii_sel
422 - const: top_netsys_sel
423 - const: top_netsys_500m_sel
424 - const: top_netsys_pao_2x_sel
425 - const: top_netsys_sync_250m_sel
426 - const: top_netsys_ppefb_250m_sel
427 - const: top_netsys_warp_sel
428 - const: xgp1
429 - const: xgp2
430 - const: xgp3
433 "^mac@[0-2]$":
437 - $ref: ethernet-controller.yaml#
442 const: mediatek,eth-mac
448 - reg
449 - compatible
452 - compatible
453 - reg
454 - interrupts
455 - clocks
456 - clock-names
457 - mediatek,ethsys
462 - |
463 #include <dt-bindings/interrupt-controller/arm-gic.h>
464 #include <dt-bindings/interrupt-controller/irq.h>
465 #include <dt-bindings/clock/mt7622-clk.h>
466 #include <dt-bindings/power/mt7622-power.h>
469 #address-cells = <2>;
470 #size-cells = <2>;
473 compatible = "mediatek,mt7622-eth";
489 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
493 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
496 cci-control-port = <&cci_control2>;
497 mediatek,pcie-mirror = <&pcie_mirror>;
499 dma-coherent;
501 #address-cells = <1>;
502 #size-cells = <0>;
504 mdio0: mdio-bus {
505 #address-cells = <1>;
506 #size-cells = <0>;
508 phy0: ethernet-phy@0 {
512 phy1: ethernet-phy@1 {
518 compatible = "mediatek,eth-mac";
519 phy-mode = "rgmii";
520 phy-handle = <&phy0>;
525 compatible = "mediatek,eth-mac";
526 phy-mode = "rgmii";
527 phy-handle = <&phy1>;
533 - |
534 #include <dt-bindings/interrupt-controller/arm-gic.h>
535 #include <dt-bindings/interrupt-controller/irq.h>
536 #include <dt-bindings/clock/mt7622-clk.h>
539 #address-cells = <2>;
540 #size-cells = <2>;
553 compatible = "mediatek,mt7986-eth";
578 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
586 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
588 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
591 #address-cells = <1>;
592 #size-cells = <0>;
594 mdio: mdio-bus {
595 #address-cells = <1>;
596 #size-cells = <0>;
598 phy5: ethernet-phy@0 {
599 compatible = "ethernet-phy-id67c9.de0a";
600 phy-mode = "2500base-x";
601 reset-gpios = <&pio 6 1>;
602 reset-deassert-us = <20000>;
606 phy6: ethernet-phy@1 {
607 compatible = "ethernet-phy-id67c9.de0a";
608 phy-mode = "2500base-x";
614 compatible = "mediatek,eth-mac";
615 phy-mode = "2500base-x";
616 phy-handle = <&phy5>;
621 compatible = "mediatek,eth-mac";
622 phy-mode = "2500base-x";
623 phy-handle = <&phy6>;