Lines Matching +full:mt7622 +full:- +full:sgmiisys
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
25 - mediatek,mt7981-eth
26 - mediatek,mt7986-eth
27 - mediatek,mt7988-eth
28 - ralink,rt5350-eth
37 clock-names:
45 power-domains:
51 reset-names:
53 - const: fe
54 - const: gmac
55 - const: ppe
62 cci-control-port: true
76 mediatek,pcie-mirror:
79 Phandle to the mediatek pcie-mirror controller.
87 mediatek,sgmiisys:
88 $ref: /schemas/types.yaml#/definitions/phandle-array
98 $ref: /schemas/types.yaml#/definitions/phandle-array
106 mediatek,wed-pcie:
109 Phandle to the mediatek wed-pcie controller.
111 dma-coherent: true
113 mdio-bus:
117 "#address-cells":
120 "#size-cells":
124 - $ref: ethernet-controller.yaml#
125 - if:
130 - mediatek,mt2701-eth
131 - mediatek,mt7623-eth
142 clock-names:
144 - const: ethif
145 - const: esw
146 - const: gp1
147 - const: gp2
153 mediatek,wed-pcie: false
158 - if:
163 - mediatek,mt7621-eth
173 clock-names:
175 - const: ethif
176 - const: fe
182 mediatek,wed-pcie: false
184 - if:
188 const: mediatek,mt7622-eth
199 clock-names:
201 - const: ethif
202 - const: esw
203 - const: gp0
204 - const: gp1
205 - const: gp2
206 - const: sgmii_tx250m
207 - const: sgmii_rx250m
208 - const: sgmii_cdr_ref
209 - const: sgmii_cdr_fb
210 - const: sgmii_ck
211 - const: eth2pll
215 mediatek,sgmiisys:
219 mediatek,wed-pcie: false
222 mediatek,pcie-mirror: false
224 - if:
228 const: mediatek,mt7629-eth
239 clock-names:
241 - const: ethif
242 - const: sgmiitop
243 - const: esw
244 - const: gp0
245 - const: gp1
246 - const: gp2
247 - const: fe
248 - const: sgmii_tx250m
249 - const: sgmii_rx250m
250 - const: sgmii_cdr_ref
251 - const: sgmii_cdr_fb
252 - const: sgmii2_tx250m
253 - const: sgmii2_rx250m
254 - const: sgmii2_cdr_ref
255 - const: sgmii2_cdr_fb
256 - const: sgmii_ck
257 - const: eth2pll
259 mediatek,sgmiisys:
265 mediatek,wed-pcie: false
267 - if:
271 const: mediatek,mt7981-eth
281 clock-names:
283 - const: fe
284 - const: gp2
285 - const: gp1
286 - const: wocpu0
287 - const: sgmii_ck
288 - const: sgmii_tx250m
289 - const: sgmii_rx250m
290 - const: sgmii_cdr_ref
291 - const: sgmii_cdr_fb
292 - const: sgmii2_tx250m
293 - const: sgmii2_rx250m
294 - const: sgmii2_cdr_ref
295 - const: sgmii2_cdr_fb
296 - const: netsys0
297 - const: netsys1
301 mediatek,sgmiisys:
305 - if:
309 const: mediatek,mt7986-eth
319 clock-names:
321 - const: fe
322 - const: gp2
323 - const: gp1
324 - const: wocpu1
325 - const: wocpu0
326 - const: sgmii_tx250m
327 - const: sgmii_rx250m
328 - const: sgmii_cdr_ref
329 - const: sgmii_cdr_fb
330 - const: sgmii2_tx250m
331 - const: sgmii2_rx250m
332 - const: sgmii2_cdr_ref
333 - const: sgmii2_cdr_fb
334 - const: netsys0
335 - const: netsys1
339 mediatek,sgmiisys:
343 - if:
347 const: mediatek,mt7988-eth
357 clock-names:
359 - const: crypto
360 - const: fe
361 - const: gp2
362 - const: gp1
363 - const: gp3
364 - const: ethwarp_wocpu2
365 - const: ethwarp_wocpu1
366 - const: ethwarp_wocpu0
367 - const: esw
368 - const: top_eth_gmii_sel
369 - const: top_eth_refck_50m_sel
370 - const: top_eth_sys_200m_sel
371 - const: top_eth_sys_sel
372 - const: top_eth_xgmii_sel
373 - const: top_eth_mii_sel
374 - const: top_netsys_sel
375 - const: top_netsys_500m_sel
376 - const: top_netsys_pao_2x_sel
377 - const: top_netsys_sync_250m_sel
378 - const: top_netsys_ppefb_250m_sel
379 - const: top_netsys_warp_sel
380 - const: xgp1
381 - const: xgp2
382 - const: xgp3
385 "^mac@[0-1]$":
389 - $ref: ethernet-controller.yaml#
394 const: mediatek,eth-mac
400 - reg
401 - compatible
404 - compatible
405 - reg
406 - interrupts
407 - clocks
408 - clock-names
409 - mediatek,ethsys
414 - |
415 #include <dt-bindings/interrupt-controller/arm-gic.h>
416 #include <dt-bindings/interrupt-controller/irq.h>
417 #include <dt-bindings/clock/mt7622-clk.h>
418 #include <dt-bindings/power/mt7622-power.h>
421 #address-cells = <2>;
422 #size-cells = <2>;
425 compatible = "mediatek,mt7622-eth";
435 <&sgmiisys CLK_SGMII_TX250M_EN>,
436 <&sgmiisys CLK_SGMII_RX250M_EN>,
437 <&sgmiisys CLK_SGMII_CDR_REF>,
438 <&sgmiisys CLK_SGMII_CDR_FB>,
441 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
445 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
447 mediatek,sgmiisys = <&sgmiisys>;
448 cci-control-port = <&cci_control2>;
449 mediatek,pcie-mirror = <&pcie_mirror>;
451 dma-coherent;
453 #address-cells = <1>;
454 #size-cells = <0>;
456 mdio0: mdio-bus {
457 #address-cells = <1>;
458 #size-cells = <0>;
460 phy0: ethernet-phy@0 {
464 phy1: ethernet-phy@1 {
470 compatible = "mediatek,eth-mac";
471 phy-mode = "rgmii";
472 phy-handle = <&phy0>;
477 compatible = "mediatek,eth-mac";
478 phy-mode = "rgmii";
479 phy-handle = <&phy1>;
485 - |
486 #include <dt-bindings/interrupt-controller/arm-gic.h>
487 #include <dt-bindings/interrupt-controller/irq.h>
488 #include <dt-bindings/clock/mt7622-clk.h>
491 #address-cells = <2>;
492 #size-cells = <2>;
505 compatible = "mediatek,mt7986-eth";
526 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
533 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
534 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
536 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
539 #address-cells = <1>;
540 #size-cells = <0>;
542 mdio: mdio-bus {
543 #address-cells = <1>;
544 #size-cells = <0>;
546 phy5: ethernet-phy@0 {
547 compatible = "ethernet-phy-id67c9.de0a";
548 phy-mode = "2500base-x";
549 reset-gpios = <&pio 6 1>;
550 reset-deassert-us = <20000>;
554 phy6: ethernet-phy@1 {
555 compatible = "ethernet-phy-id67c9.de0a";
556 phy-mode = "2500base-x";
562 compatible = "mediatek,eth-mac";
563 phy-mode = "2500base-x";
564 phy-handle = <&phy5>;
569 compatible = "mediatek,eth-mac";
570 phy-mode = "2500base-x";
571 phy-handle = <&phy6>;