Lines Matching +full:fifo +full:- +full:depth
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 max-speed:
24 nvmem-cells:
29 nvmem-cell-names:
30 const: mac-address
32 phy-connection-type:
40 - internal
41 - mii
42 - mii-lite
43 - gmii
44 - sgmii
45 - psgmii
46 - qsgmii
47 - qusgmii
48 - tbi
49 - rev-mii
50 - rmii
51 - rev-rmii
52 - moca
55 - rgmii
59 - rgmii-id
62 - rgmii-rxid
65 - rgmii-txid
66 - rtbi
67 - smii
68 - xgmii
69 - trgmii
70 - 1000base-x
71 - 2500base-x
72 - 5gbase-r
73 - rxaui
74 - xaui
76 # 10GBASE-KR, XFI, SFI
77 - 10gbase-kr
78 - usxgmii
79 - 10gbase-r
80 - 25gbase-r
81 - 10g-qxgmii
83 phy-mode:
84 $ref: "#/properties/phy-connection-type"
86 pcs-handle:
87 $ref: /schemas/types.yaml#/definitions/phandle-array
92 bus to link with an external PHY (phy-handle) if exists.
94 pcs-handle-names:
96 The name of each PCS in pcs-handle.
98 phy-handle:
104 $ref: "#/properties/phy-handle"
107 phy-device:
108 $ref: "#/properties/phy-handle"
111 rx-fifo-depth:
114 The size of the controller\'s receive fifo in bytes. This is used
115 for components that can have configurable receive fifo sizes,
124 tx-fifo-depth:
127 The size of the controller\'s transmit fifo in bytes. This
128 is used for components that can have configurable fifo sizes.
132 Specifies the PHY management type. If auto is set and fixed-link
137 - auto
138 - in-band-status
140 fixed-link:
142 - $ref: /schemas/types.yaml#/definitions/uint32-array
145 - minimum: 0
149 specified fixed-links
151 - enum: [0, 1]
156 - enum: [10, 100, 1000, 2500, 10000]
160 - enum: [0, 1]
164 - enum: [0, 1]
168 - type: object
177 full-duplex:
180 Indicates that full-duplex is used. When absent, half
188 asym-pause:
193 link-gpios:
199 - speed
211 '#address-cells':
214 '#size-cells':
218 '^led@[a-f0-9]+$':
230 - reg
237 pcs-handle-names: [pcs-handle]
240 - $ref: /schemas/net/network-class.yaml#
241 - if:
243 phy-mode:
246 - rgmii
247 - rgmii-rxid
248 - rgmii-txid
249 - rgmii-id
252 rx-internal-delay-ps:
257 tx-internal-delay-ps:
268 # 'phy-modes' & 'phy-connection-type' properties 'rgmii', 'rgmii-id',
269 # 'rgmii-rxid', and 'rgmii-txid' are frequently used wrongly by
282 # 'rgmii-id' should be used. Here, 'id' refers to 'internal delay',
286 # lines, either 'rgmii-rxid' or 'rgmii-txid' should be used,
295 # any RGMII phy mode other than 'rgmii-id' is probably wrong, and is
312 # to read the 'phy-mode' from Device Tree, not implement any delays,
314 # specified by the 'phy-mode'. The PHY should always be reconfigured
325 # delays which cannot be disabled. The 'phy-mode' only describes the
327 # the meaning of 'phy-mode'. It does however mean that a 'phy-mode' of
333 # must modify the phy-mode it passes to the PHY, removing the delay it
335 # non-functioning link.
339 # properties 'rx-internal-delay-ps' and 'tx-internal-delay-ps' should
341 # expected here are small. A value of 2000ps, i.e 2ns, and a phy-mode
345 # 'rx-internal-delay-ps' and 'tx-internal-delay-ps' in the PHY node
346 # should be used. When the PHY is implementing delays, e.g. 'rgmii-id'