Lines Matching +full:pcie +full:- +full:phy2
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
19 SPI or PCIe. The present DSA binding shall be used when the host controlling
22 Frame DMA or register-based I/O.
26 This is found in the NXP T1040, where it is a memory-mapped platform
31 - phy-mode = "internal": on ports 8 and 9
32 - phy-mode = "sgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
33 - phy-mode = "qsgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
34 - phy-mode = "1000base-x": on ports 0, 1, 2, 3, 4, 5, 6, 7
39 enetc root complex. As a result, the ethernet-switch node is a sub-node of
40 the PCIe root complex node and its "reg" property conforms to the parent
50 - phy-mode = "internal": on ports 4 and 5
51 - phy-mode = "sgmii": on ports 0, 1, 2, 3
52 - phy-mode = "qsgmii": on ports 0, 1, 2, 3
53 - phy-mode = "usxgmii": on ports 0, 1, 2, 3
54 - phy-mode = "1000base-x": on ports 0, 1, 2, 3
55 - phy-mode = "2500base-x": on ports 0, 1, 2, 3
60 - mscc,vsc9953-switch
61 - pci1957,eef0
73 little-endian: true
74 big-endian: true
77 - compatible
78 - reg
81 - $ref: dsa.yaml#/$defs/ethernet-ports
82 - if:
88 - interrupts
94 - |
95 #include <dt-bindings/interrupt-controller/arm-gic.h>
97 pcie { /* Integrated Endpoint Root Complex */
98 #address-cells = <3>;
99 #size-cells = <2>;
101 ethernet-switch@0,5 {
106 ethernet-ports {
107 #address-cells = <1>;
108 #size-cells = <0>;
112 phy-mode = "qsgmii";
113 phy-handle = <&phy0>;
114 managed = "in-band-status";
119 phy-mode = "qsgmii";
120 phy-handle = <&phy1>;
121 managed = "in-band-status";
126 phy-mode = "qsgmii";
127 phy-handle = <&phy2>;
128 managed = "in-band-status";
133 phy-mode = "qsgmii";
134 phy-handle = <&phy3>;
135 managed = "in-band-status";
141 phy-mode = "internal";
143 fixed-link {
145 full-duplex;
153 phy-mode = "internal";
155 fixed-link {
157 full-duplex;
165 - |
167 #address-cells = <1>;
168 #size-cells = <1>;
170 ethernet-switch@800000 {
171 compatible = "mscc,vsc9953-switch";
173 little-endian;
175 ethernet-ports {
176 #address-cells = <1>;
177 #size-cells = <0>;
181 phy-mode = "qsgmii";
182 phy-handle = <&phy0>;
183 managed = "in-band-status";
188 phy-mode = "qsgmii";
189 phy-handle = <&phy1>;
190 managed = "in-band-status";
195 phy-mode = "qsgmii";
196 phy-handle = <&phy2>;
197 managed = "in-band-status";
202 phy-mode = "qsgmii";
203 phy-handle = <&phy3>;
204 managed = "in-band-status";
209 phy-mode = "qsgmii";
210 phy-handle = <&phy4>;
211 managed = "in-band-status";
216 phy-mode = "qsgmii";
217 phy-handle = <&phy5>;
218 managed = "in-band-status";
223 phy-mode = "qsgmii";
224 phy-handle = <&phy6>;
225 managed = "in-band-status";
230 phy-mode = "qsgmii";
231 phy-handle = <&phy7>;
232 managed = "in-band-status";
237 phy-mode = "internal";
240 fixed-link {
242 full-duplex;
249 phy-mode = "internal";
252 fixed-link {
254 full-duplex;