Lines Matching +full:multi +full:- +full:port
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
20 MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN,
23 The MT7988 SoC comes with a built-in switch similar to MT7531 as well as four
26 CPU port and 4 user ports connected to the built-in Gigabit Ethernet PHYs.
34 Port 5 on MT7530 supports various configurations:
36 - Port 5 can be used as a CPU port.
38 - PHY 0 or 4 of the switch can be muxed to gmac5 of the switch. Therefore,
39 the gmac of the SoC which is wired to port 5 can connect to the PHY.
40 This is usually used for connecting the wan port directly to the CPU to
43 The driver looks up the reg on the ethernet-phy node, which the phy-handle
46 The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the
48 MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this.
54 - For the multi-chip module MT7530, in case of an external phy wired to
55 gmac1 of the SoC, port 5 must not be enabled.
63 - Port 5 can be wired to an external phy. Port 5 becomes a DSA user port.
65 For the multi-chip module MT7530, the external phy must be wired TX to TX
69 For the multi-chip module MT7530, muxing PHY 0 or 4 won't work when the
79 - description:
80 Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC
83 - description:
87 - description:
88 Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs
91 - description:
92 Built-in switch of the MT7988 SoC
93 const: mediatek,mt7988-switch
95 - description:
96 Built-in switch of the Airoha EN7581 SoC
97 const: airoha,en7581-switch
102 core-supply:
106 "#gpio-cells":
109 gpio-controller:
115 port 0 LED 0..2 as GPIO 0..2
116 port 1 LED 0..2 as GPIO 3..5
117 port 2 LED 0..2 as GPIO 6..8
118 port 3 LED 0..2 as GPIO 9..11
119 port 4 LED 0..2 as GPIO 12..14
121 "#interrupt-cells":
124 interrupt-controller: true
129 io-supply:
132 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for
139 switch is a part of the multi-chip module.
141 reset-gpios:
149 reset-names:
159 "^(ethernet-)?ports$":
164 "^(ethernet-)?port@[0-6]$":
171 Port address described must be 5 or 6 for CPU port and from 0 to 5
175 - if:
181 - 5
182 - 6
185 - compatible
186 - reg
189 mt7530-dsa-port:
191 "^(ethernet-)?ports$":
193 "^(ethernet-)?port@[0-6]$":
203 phy-mode:
205 - gmii
206 - mii
207 - rgmii
210 phy-mode:
212 - rgmii
213 - trgmii
215 mt7531-dsa-port:
217 "^(ethernet-)?ports$":
219 "^(ethernet-)?port@[0-6]$":
229 phy-mode:
231 - 1000base-x
232 - 2500base-x
233 - rgmii
234 - sgmii
237 phy-mode:
239 - 1000base-x
240 - 2500base-x
241 - sgmii
244 - $ref: dsa.yaml#/$defs/ethernet-ports
245 - if:
247 - mediatek,mcm
250 reset-gpios: false
253 - resets
254 - reset-names
256 - dependencies:
257 interrupt-controller: [ interrupts ]
259 - if:
264 $ref: "#/$defs/mt7530-dsa-port"
266 - core-supply
267 - io-supply
269 - if:
274 $ref: "#/$defs/mt7531-dsa-port"
276 gpio-controller: false
279 - if:
284 $ref: "#/$defs/mt7530-dsa-port"
286 - mediatek,mcm
288 - if:
292 - mediatek,mt7988-switch
293 - airoha,en7581-switch
295 $ref: "#/$defs/mt7530-dsa-port"
297 gpio-controller: false
299 reset-names: false
305 - |
306 #include <dt-bindings/gpio/gpio.h>
309 #address-cells = <1>;
310 #size-cells = <0>;
316 reset-gpios = <&pio 33 0>;
318 core-supply = <&mt6323_vpa_reg>;
319 io-supply = <&mt6323_vemc3v3_reg>;
321 ethernet-ports {
322 #address-cells = <1>;
323 #size-cells = <0>;
325 port@0 {
330 port@1 {
335 port@2 {
340 port@3 {
345 port@4 {
350 port@6 {
353 phy-mode = "rgmii";
355 fixed-link {
357 full-duplex;
366 - |
367 #include <dt-bindings/reset/mt2701-resets.h>
370 #address-cells = <1>;
371 #size-cells = <0>;
379 reset-names = "mcm";
381 core-supply = <&mt6323_vpa_reg>;
382 io-supply = <&mt6323_vemc3v3_reg>;
384 ethernet-ports {
385 #address-cells = <1>;
386 #size-cells = <0>;
388 port@0 {
393 port@1 {
398 port@2 {
403 port@3 {
408 port@4 {
413 port@6 {
416 phy-mode = "trgmii";
418 fixed-link {
420 full-duplex;
429 - |
430 #include <dt-bindings/gpio/gpio.h>
431 #include <dt-bindings/interrupt-controller/irq.h>
434 #address-cells = <1>;
435 #size-cells = <0>;
441 reset-gpios = <&pio 54 0>;
443 interrupt-controller;
444 #interrupt-cells = <1>;
445 interrupt-parent = <&pio>;
448 ethernet-ports {
449 #address-cells = <1>;
450 #size-cells = <0>;
452 port@0 {
457 port@1 {
462 port@2 {
467 port@3 {
472 port@4 {
477 port@6 {
480 phy-mode = "2500base-x";
482 fixed-link {
484 full-duplex;
493 - |
494 #include <dt-bindings/interrupt-controller/mips-gic.h>
495 #include <dt-bindings/reset/mt7621-reset.h>
498 #address-cells = <1>;
499 #size-cells = <0>;
507 reset-names = "mcm";
509 interrupt-controller;
510 #interrupt-cells = <1>;
511 interrupt-parent = <&gic>;
514 ethernet-ports {
515 #address-cells = <1>;
516 #size-cells = <0>;
518 port@0 {
523 port@1 {
528 port@2 {
533 port@3 {
538 port@4 {
543 port@6 {
546 phy-mode = "trgmii";
548 fixed-link {
550 full-duplex;
559 - |
560 #include <dt-bindings/interrupt-controller/mips-gic.h>
561 #include <dt-bindings/reset/mt7621-reset.h>
564 #address-cells = <1>;
565 #size-cells = <0>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&rgmii2_pins>;
571 compatible = "mediatek,eth-mac";
574 phy-mode = "rgmii";
575 phy-handle = <&example5_ethphy4>;
579 #address-cells = <1>;
580 #size-cells = <0>;
583 example5_ethphy4: ethernet-phy@4 {
593 reset-names = "mcm";
595 interrupt-controller;
596 #interrupt-cells = <1>;
597 interrupt-parent = <&gic>;
600 ethernet-ports {
601 #address-cells = <1>;
602 #size-cells = <0>;
604 port@0 {
609 port@1 {
614 port@2 {
619 port@3 {
625 port@4 {
631 port@6 {
634 phy-mode = "trgmii";
636 fixed-link {
638 full-duplex;
648 - |
649 #include <dt-bindings/interrupt-controller/mips-gic.h>
650 #include <dt-bindings/reset/mt7621-reset.h>
653 #address-cells = <1>;
654 #size-cells = <0>;
656 pinctrl-names = "default";
657 pinctrl-0 = <&rgmii2_pins>;
660 compatible = "mediatek,eth-mac";
663 phy-mode = "rgmii";
664 phy-handle = <&example6_ethphy7>;
668 #address-cells = <1>;
669 #size-cells = <0>;
672 example6_ethphy7: ethernet-phy@7 {
674 phy-mode = "rgmii";
683 reset-names = "mcm";
685 interrupt-controller;
686 #interrupt-cells = <1>;
687 interrupt-parent = <&gic>;
690 ethernet-ports {
691 #address-cells = <1>;
692 #size-cells = <0>;
694 port@0 {
699 port@1 {
704 port@2 {
709 port@3 {
714 port@4 {
719 port@6 {
722 phy-mode = "trgmii";
724 fixed-link {
726 full-duplex;
735 # Example 7: MT7621: mux external phy to MT7530's port 5
736 - |
737 #include <dt-bindings/interrupt-controller/mips-gic.h>
738 #include <dt-bindings/reset/mt7621-reset.h>
741 #address-cells = <1>;
742 #size-cells = <0>;
744 pinctrl-names = "default";
745 pinctrl-0 = <&rgmii2_pins>;
748 #address-cells = <1>;
749 #size-cells = <0>;
752 example7_ethphy7: ethernet-phy@7 {
754 phy-mode = "rgmii";
763 reset-names = "mcm";
765 interrupt-controller;
766 #interrupt-cells = <1>;
767 interrupt-parent = <&gic>;
770 ethernet-ports {
771 #address-cells = <1>;
772 #size-cells = <0>;
774 port@0 {
779 port@1 {
784 port@2 {
789 port@3 {
794 port@4 {
799 port@5 {
802 phy-mode = "rgmii-txid";
803 phy-handle = <&example7_ethphy7>;
806 port@6 {
809 phy-mode = "trgmii";
811 fixed-link {
813 full-duplex;